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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N SKUs
......................................................................
Patch Set 6:
(4 comments)
Patchset:
PS6:
All comments incorporated
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/64472/comment/7693428f_7cfb5f3c
PS2, Line 33: ADL_N_081_15W_CORE,
> Please give tab here.
Done
https://review.coreboot.org/c/coreboot/+/64472/comment/2029dfa3_49dad0dc
PS2, Line 34: ADL_N_041_6W_CORE,
> Same above comment here.
Done
https://review.coreboot.org/c/coreboot/+/64472/comment/b22c43a7_4e0ccd1b
PS2, Line 35: ADL_N_021_6W_CORE,
> same above comment here.
Done
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Change subject: mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUs
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Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/variants/nereid: Add DPTF passive and critical policies for Nereid
......................................................................
Patch Set 7: Verified+1
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150179):
https://review.coreboot.org/c/coreboot/+/64468/comment/8016e144_74dba273
PS7, Line 11: Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150179):
https://review.coreboot.org/c/coreboot/+/64468/comment/5cebff90_62cf9353
PS7, Line 12: Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Change subject: mb/google/brya/variants/nereid: Add DPTF passive and critical policies for Nereid
......................................................................
Patch Set 7:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64468/comment/212ab3f8_8784713c
PS5, Line 8:
> Add "BUG=" information if any. If no bug available then mention it as "None".
Done
https://review.coreboot.org/c/coreboot/+/64468/comment/9e5ad918_a682d15a
PS5, Line 10: Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
> Possible unwrapped commit description (prefer a maximum 72 chars per line)
Please fix.
https://review.coreboot.org/c/coreboot/+/64468/comment/9028aebd_4f4f08b7
PS5, Line 11: Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
> Possible unwrapped commit description (prefer a maximum 72 chars per line)
Please fix.
Patchset:
PS7:
All comments are resolved
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Hello Jesper Lin, build bot (Jenkins), Tim Wawrzynczak, Sumeet R Pawnikar, Vidya Gopalakrishnan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64468
to look at the new patch set (#6).
Change subject: mb/google/brya/variants/nereid: Add DPTF passive and critical policies for Nereid
......................................................................
mb/google/brya/variants/nereid: Add DPTF passive and critical policies for Nereid
BUG=b:233030505
BRANCH=NoneTEST=Build FW and test on Nereid board.
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
Change-Id: I195f4b507ee57948751f0119735d8350dfce984b
---
M src/mainboard/google/brya/variants/nereid/overridetree.cb
1 file changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/64468/6
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Change subject: spd/lp5: Add SPD for Micron MT62F1G32D4DS
......................................................................
Patch Set 5: Code-Review+1
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Change subject: Documentation: Update coreboot 4.17 release notes
......................................................................
Patch Set 3: Code-Review+1
(4 comments)
File Documentation/releases/coreboot-4.17-relnotes.md:
https://review.coreboot.org/c/coreboot/+/64846/comment/f97d5046_6de7345e
PS3, Line 141: (because it is part of another firmware section (IFWI or a different
: CBFS), the CRTM measurement fails.
A closing bracket is missing here.
https://review.coreboot.org/c/coreboot/+/64846/comment/8ae5d159_c3958658
PS3, Line 155: Refer AMD PSB user guide
Refer _to_ AMD PSB user guide?
https://review.coreboot.org/c/coreboot/+/64846/comment/9d9ac4ef_688acf02
PS3, Line 169: the
remove?
https://review.coreboot.org/c/coreboot/+/64846/comment/ec7d8338_72947eb1
PS3, Line 322: the virtually
: the same
one 'the' extra?
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Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63942/comment/6963ddef_1ffb2dbc
PS6, Line 671: if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
double negation is unnecessary in a if statement.
However, you could also write it:
s_cfg->PcieRpSlotImplemented[i] = !(rp_cfg->flags & PCIE_RP_BUILT_IN)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/63942/comment/fec24130_2b575261
PS6, Line 30: /* indicates that this root port is built-in */
missing ending dot character.
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