coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload: Add CONFIG_LP_ELOG and its dependency
by Hsuan-ting Chen (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63115 ) Change subject: libpayload: Add CONFIG_LP_ELOG and its dependency ...................................................................... Patch Set 9: (1 comment) File payloads/libpayload/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63115/comment/fd729b0e_a8d39433 PS9, Line 51: classes-$(CONFIG_LP_ELOG) += elog > libc As Yu-ping mentioned, we've tried to add it into libc but elog was actually not really related to core c library. Adding libutil might be another good choice, I would think some other things e.g. fmap.c code also consider as a 'util', WDYT? > Kconfig Though it is still a small file only, I am not sure if we should prevent including it for the non-ChromeOS platforms since I am not familiar with them. If you think it is okay to unconditionally adding it now (and no plan to enlarge it yet), I will change it. -- To view, visit https://review.coreboot.org/c/coreboot/+/63115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Gerrit-Change-Number: 63115 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 03:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/rex: Add memory init
by Eric Lai (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tarun Tuli, Tim Wawrzynczak, Kapil Porwal, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Tim Wawrzynczak, Kapil Porwal, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64850 to look at the new patch set (#2). Change subject: mb/google/rex: Add memory init ...................................................................... mb/google/rex: Add memory init Add memory init with placeholder. DQ map can be auto probed by fsp. So leave it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade --- M src/mainboard/google/rex/romstage.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc A src/mainboard/google/rex/variants/baseboard/rex/memory.c A src/mainboard/google/rex/variants/rex0/memory/Makefile.inc A src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt 7 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64850/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Gerrit-Change-Number: 64850 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/nereid: Add ACPI _PLD custom values
by 9elements QA (Code Review) 01 Jun '22

01 Jun '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64729 ) Change subject: mb/google/brya/var/nereid: Add ACPI _PLD custom values ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/106806 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/106805 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/106804 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/106803 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/106802 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/106801 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/106800 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/106799 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/106798 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/106797 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/106796 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/106795 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/64729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Gerrit-Change-Number: 64729 Gerrit-PatchSet: 3 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 03:23:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/rex: Add memory init
by Eric Lai (Code Review) 01 Jun '22

01 Jun '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64850 ) Change subject: mb/google/rex: Add memory init ...................................................................... mb/google/rex: Add memory init Add memory init with placeholder. DQ map can be auto probed by fsp. So leave it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade --- M src/mainboard/google/rex/romstage.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc A src/mainboard/google/rex/variants/baseboard/rex/memory.c A src/mainboard/google/rex/variants/rex0/memory/Makefile.inc A src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt 7 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64850/1 diff --git a/src/mainboard/google/rex/romstage.c b/src/mainboard/google/rex/romstage.c index a993d14..9e41d46 100644 --- a/src/mainboard/google/rex/romstage.c +++ b/src/mainboard/google/rex/romstage.c @@ -3,12 +3,21 @@ #include <baseboard/variants.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <string.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; size_t pads_num; + const struct mb_cfg *mem_config = variant_memory_params(); + bool half_populated = variant_is_half_populated(); + struct mem_spd spd_info; pads = variant_romstage_gpio_table(&pads_num); gpio_configure_pads(pads, pads_num); + + memset(&spd_info, 0, sizeof(spd_info)); + variant_get_spd_info(&spd_info); + + memcfg_init(memupd, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index c2dbe54..6fd64c9 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -15,4 +16,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); +const struct mb_cfg *variant_memory_params(void); +void variant_get_spd_info(struct mem_spd *spd_info); +int variant_memory_sku(void); +bool variant_is_half_populated(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc index 6c29346..7d1f886 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc +++ b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/baseboard/rex/memory.c b/src/mainboard/google/rex/variants/baseboard/rex/memory.c new file mode 100644 index 0000000..c10d470 --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/rex/memory.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + return 0; +} + +bool __weak variant_is_half_populated(void) +{ + return 0; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc b/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc new file mode 100644 index 0000000..0016256 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 0(0b0000) diff --git a/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt new file mode 100644 index 0000000..a329cca --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! + +DRAM Part Name ID to assign +empty 0 (0000) + diff --git a/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt new file mode 100644 index 0000000..c8a24cc --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:F +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +MT53E2G32D4NQ-046 WT:A +H9HCNNNCPMMLXR-NEE +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/64850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Gerrit-Change-Number: 64850 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd/lp5: Add SPD for Micron MT62F1G32D4DS
by Caveh Jalali (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Caveh Jalali, Nick Vaccaro. Hello build bot (Jenkins), Jack Rosenthal, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64733 to look at the new patch set (#5). Change subject: spd/lp5: Add SPD for Micron MT62F1G32D4DS ...................................................................... spd/lp5: Add SPD for Micron MT62F1G32D4DS This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-6.hex M spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-6.hex 5 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/64733/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/64733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Gerrit-Change-Number: 64733 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Add CONFIG_LP_ELOG and its dependency
by Yu-Ping Wu (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Hsuan-ting Chen, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63115 ) Change subject: libpayload: Add CONFIG_LP_ELOG and its dependency ...................................................................... Patch Set 9: (1 comment) File payloads/libpayload/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63115/comment/ac2f90ad_25de9b7c PS9, Line 51: classes-$(CONFIG_LP_ELOG) += elog > It seems overkill to create a Kconfig and a whole extra library for such a small file. […] Rocco did that in PS3. However, in my opinion the elog utility doesn't seem to belong to libc (and any existing libs). If there are more stuff like elog in the future, do we want to add them all to libc? I wonder if we can create a separate lib `libutil` for all these small utilities. We can keep the `elog` class name for now, but I'll rename it when there are more utilities coming. -- To view, visit https://review.coreboot.org/c/coreboot/+/63115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Gerrit-Change-Number: 63115 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 03:00:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: spd/lp5: Add SPD for Micron MT62F1G32D4DS
by Caveh Jalali (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Caveh Jalali, Nick Vaccaro. Hello build bot (Jenkins), Jack Rosenthal, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64733 to look at the new patch set (#4). Change subject: spd/lp5: Add SPD for Micron MT62F1G32D4DS ...................................................................... spd/lp5: Add SPD for Micron MT62F1G32D4DS This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-6.hex M spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-6.hex 5 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/64733/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Gerrit-Change-Number: 64733 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Update qc_blobs submodule to upstream master
by Shelley Chen (Code Review) 01 Jun '22

01 Jun '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64844 ) Change subject: Update qc_blobs submodule to upstream master ...................................................................... Update qc_blobs submodule to upstream master Updating from commit id 9ab0f0b: sc7280: Update AOP firmware to version 379 to commit id e8efa5d: sc7180/boot: Update qclib blobs binaries from 44 to 46 This brings in 7 new commits. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5f0a9075cde90991e927f3bfb75246bdb9877837 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64844 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M 3rdparty/qc_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 9ab0f0b..e8efa5d 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 9ab0f0b71c25aa8414e72040bad6fe12b0ccb3f3 +Subproject commit e8efa5d98dd5bb4662bc575b7ef2104d2aff9277 -- To view, visit https://review.coreboot.org/c/coreboot/+/64844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0a9075cde90991e927f3bfb75246bdb9877837 Gerrit-Change-Number: 64844 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: spd/lp5: add new MT62F1G32D4DS
by Caveh Jalali (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Caveh Jalali, Nick Vaccaro. Hello build bot (Jenkins), Jack Rosenthal, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64733 to look at the new patch set (#3). Change subject: spd/lp5: add new MT62F1G32D4DS ...................................................................... spd/lp5: add new MT62F1G32D4DS This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-6.hex M spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-6.hex 5 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/64733/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Gerrit-Change-Number: 64733 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Update qc_blobs submodule to upstream master
by Shelley Chen (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64844 ) Change subject: Update qc_blobs submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0a9075cde90991e927f3bfb75246bdb9877837 Gerrit-Change-Number: 64844 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 02:56:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2022