coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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6166 discussions

Change in coreboot[master]: libpayload/nvme: Fix controller disablement in (de)init sequence
by Nico Huber (Code Review) 02 May '22

02 May '22

Attention is currently required from: Thomas Heijligen. Hello build bot (Jenkins), Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63935 to look at the new patch set (#3). Change subject: libpayload/nvme: Fix controller disablement in (de)init sequence ...................................................................... libpayload/nvme: Fix controller disablement in (de)init sequence We wrote to the wrong register. The EN bit is in the CC (Controller Configuration) register at 0x14. Fixes re-initialization in QEMU and on siemens/chili during a second FILO run. Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/drivers/storage/nvme.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63935/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8 Gerrit-Change-Number: 63935 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
by Tim Wawrzynczak (Code Review) 02 May '22

02 May '22

Attention is currently required from: Subrata Banik, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63953 ) Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63953/comment/45909367_1d48dd2b PS1, Line 10: > > What are the consequences of doing this? What does the PMC do differently? […] Ack File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/63953/comment/5bfd3ab8_15c2e199 PS2, Line 798: if (pmc_send_ipc_cmd(cmd, &req, &rsp) == CB_SUCCESS) : return; : : printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); nit: ``` if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77d428f9501feaccab8bb431090d10ce8d3af9b2 Gerrit-Change-Number: 63953 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 02 May 2022 19:58:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
by Michael Niewöhner (Code Review) 02 May '22

02 May '22

Attention is currently required from: Michał Kopeć, Angel Pons, Krystian Hebel. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62495 ) Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops ...................................................................... Patch Set 5: (1 comment) File src/ec/clevo/it5570/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/62495/comment/cb330645_a442905c PS5, Line 100: Method (I2ER, 1, NotSerialized) > +1 will be gone in the combined implementation (3mdeb and mine), since it's just for debugging -- To view, visit https://review.coreboot.org/c/coreboot/+/62495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c7d1d4f86d764bd10cfa3b0da23d1116281f3b Gerrit-Change-Number: 62495 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Mon, 02 May 2022 19:53:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by Michael Niewöhner (Code Review) 02 May '22

02 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... Patch Set 5: (3 comments) File src/mainboard/clevo/tgl-u/bootblock.c: https://review.coreboot.org/c/coreboot/+/62498/comment/f97fcec0_3567de21 PS1, Line 16: if (onoff) { : gpio_set(DGPU_RST_N, 0); : mdelay(4); : gpio_set(DGPU_PWR_EN, 1); : mdelay(4); : gpio_set(DGPU_RST_N, 1); : } else { : gpio_set(DGPU_RST_N, 0); : mdelay(4); : gpio_set(DGPU_PWR_EN, 0); > Also, no polling for PWROK/PG to assert before releasing dGPU reset? the gpios might be mb specific; we still have APIs to handle that in a generic way File src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/fea18805_5bddf0d1 PS3, Line 4: # TODO: Check if this is correct it's not wrong, but the fans should be powerful enough to handle way more power https://review.coreboot.org/c/coreboot/+/62498/comment/6e233411_ff13aab3 PS3, Line 42: register "HybridStorageMode" = "0" not needed, 0 is the default -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 02 May 2022 19:51:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
by Prashant Malani (Code Review) 02 May '22

02 May '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63793 ) Change subject: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn ...................................................................... Patch Set 1: (2 comments) File src/acpi/acpigen_usb.c: https://review.coreboot.org/c/coreboot/+/63793/comment/f6566f61_11739337 PS1, Line 109: retimer-switch > As long as that is the only change expected, I don't foresee that being a problem. Ack File src/include/acpi/acpigen_usb.h: https://review.coreboot.org/c/coreboot/+/63793/comment/709865c6_c57f220f PS1, Line 46: * various endpoints (xHCI, DP, etc.) on the SoC. > copy pasta ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Gerrit-Change-Number: 63793 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 May 2022 19:48:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
by Prashant Malani (Code Review) 02 May '22

02 May '22

Attention is currently required from: Lance Zhao. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63793 to look at the new patch set (#2). Change subject: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn ...................................................................... ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn Some platforms have retimers which can be configured via the EC. Add a handle to these retimer devices to the Type C connector device, using devicetree references. Add the handles to the Type C port device on brya0 to ensure things get build tested. BUG=b:208883648 TEST=Verify disassembled SSDT on brya. BRANCH=None Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e --- M src/acpi/acpigen_usb.c M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_usb.h M src/mainboard/google/brya/variants/brya0/overridetree.cb 5 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63793/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Gerrit-Change-Number: 63793 Gerrit-PatchSet: 2 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google/chromeec: Add EC Mux device
by Prashant Malani (Code Review) 02 May '22

02 May '22

Attention is currently required from: Paul Menzel, Prashant Malani. Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63792 to look at the new patch set (#2). Change subject: ec/google/chromeec: Add EC Mux device ...................................................................... ec/google/chromeec: Add EC Mux device Introduce an EC Mux ACPI device, which will control retimer and discrete (off-AP) mux configuration. Add entries to the devicetree override for brya0 to ensure the new driver gets build tested. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Signed-off-by: Prashant Malani <pmalani(a)chromium.org> --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/mux/Kconfig A src/ec/google/chromeec/mux/Makefile.inc A src/ec/google/chromeec/mux/conn/Makefile.inc A src/ec/google/chromeec/mux/conn/conn.c A src/ec/google/chromeec/mux/mux.c M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brya0/overridetree.cb 8 files changed, 115 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63792/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Gerrit-Change-Number: 63792 Gerrit-PatchSet: 2 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tarun Tuli (Code Review) 02 May '22

02 May '22

Attention is currently required from: Subrata Banik, Paul Menzel. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 12: (4 comments) File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/63969/comment/1691398d_8fe89fce PS12, Line 179: min_pci_d_states > wondering if we have any way to reduce this static array. […] Yes we could instead add statements for each device to populate at run time if we feel that improves clarity/readability. I'm somewhat indifferent on which may be cleaner so am open to the consensus. In your second suggestion, are you proposing to include the D-states within the devicetree itself and propagating those up? https://review.coreboot.org/c/coreboot/+/63969/comment/818b0aeb_32964f1f PS12, Line 470: > does it make sense to check if device is actually enabled or not ? if not then set to `undef`? For clarification, we basically won't emit anything if the device is not enabled. Although the structure has an enabled field, it isn't really used for us. Tim and I did discuss briefly and decided it would be cleaner than have a table also filled with disabled devices as it doesn't add much to the insight of our LPM constraints. https://review.coreboot.org/c/coreboot/+/63969/comment/c241b9fb_b0113d78 PS12, Line 524: if (min_state == UNDEF) : min_state = D0; > looks like you are setting min_state = D0 for all devices with UNDEF ? in that case, do we still nee […] The way I probably should have handled this is soc_lpi_include_device() should check for this condition (e.g. a device is enabled, but doesn't have it's D-state defined) and return false if that scenario. In that way, we shouldn't emit anything for that particular device and likely should just report a error instead. File src/soc/intel/common/block/acpi/pep.c: https://review.coreboot.org/c/coreboot/+/63969/comment/86f08892_f14d3eb2 PS12, Line 115: /* SoC returned more than zero devices so use those. */ : printk(BIOS_INFO, "Returning SoC specific constraint package for %d devices\n", num_devices) > is this for debug purpose ? Yes. Will just show on boot how many devices we have emitted in this table. -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 12 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 02 May 2022 19:46:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines
by Lean Sheng Tan (Code Review) 02 May '22

02 May '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Morgan Jang, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63989 ) Change subject: mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5 Gerrit-Change-Number: 63989 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 May 2022 19:42:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi: Consolidate POST code handling
by Lean Sheng Tan (Code Review) 02 May '22

02 May '22

Attention is currently required from: Lance Zhao, Angel Pons. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63988 ) Change subject: arch/x86/acpi: Consolidate POST code handling ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Gerrit-Change-Number: 63988 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 02 May 2022 19:39:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2022