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Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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Change subject: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
......................................................................
ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani(a)chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
---
M src/acpi/acpigen_usb.c
M src/ec/google/chromeec/chip.h
M src/ec/google/chromeec/ec_acpi.c
M src/include/acpi/acpigen_usb.h
4 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63793/3
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Gerrit-Change-Number: 63793
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Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63792
to look at the new patch set (#3).
Change subject: ec/google/chromeec: Add EC Mux device
......................................................................
ec/google/chromeec: Add EC Mux device
Introduce an EC Mux ACPI device, which will control retimer and discrete
(off-AP) mux configuration.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8
Signed-off-by: Prashant Malani <pmalani(a)chromium.org>
---
M src/ec/google/chromeec/Makefile.inc
A src/ec/google/chromeec/mux/Kconfig
A src/ec/google/chromeec/mux/Makefile.inc
A src/ec/google/chromeec/mux/conn/Makefile.inc
A src/ec/google/chromeec/mux/conn/conn.c
A src/ec/google/chromeec/mux/mux.c
6 files changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63792/3
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63982 )
Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 1: -Code-Review
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/72dd7a51_5162703c
PS1, Line 117: spi_fill_ssdt
Hmm don't you want to do this only when the device cannot be enumerated?
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Change subject: utils/cbfstool: Disable Wstrict-prototypes warning
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > Can the LZ4 code be updated instead? […]
I don't want the LZ4 code to diverge from upstream. If someone has time to fix this upstream (if it hasn't already) and then pull back and test an uprev here, they're welcome to do that and we can revert this again. Until then I think this is a reasonable solution. There's no reason for us to waste extra time on warnings about stuff in code that a) has always been there to begin with (and is only now getting called out because of clang's questionable over-interpretations of long-standing warning settings) and b) we don't plan to do any independent development on anyway (so what's even the point in warning about style stuff in code that doesn't change).
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/42ea78c7_99d48d47
PS12, Line 524: if (min_state == UNDEF)
: min_state = D0;
> The way I probably should have handled this is soc_lpi_include_device() should check for this condit […]
Implemented in Patch set #13. I think the logic is clearer/more correct this way.
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#13).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 410 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/13
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Change subject: mb/google/skyrim/var/skyrim: Add VL822 external USB hub
......................................................................
Patch Set 4:
This change is ready for review.
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