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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/c166943c_7a27abce
PS6, Line 261: Pantone ROM
> I wonder what this EEPROM is used for.
Some models ship with a Pantone-validated display. I think this ROM stores the certification data, but I don't have a way to test this
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/14a96780_11405fa9
PS6, Line 9: * Disable AER for the SSD slot to support S0ix with SSDs running
: * buggy firmware
:
> any more details on this?
Samsung 980 (non-pro) SSD causes the laptop to fail to wake from s0ix standby while AER is enabled. Vendor firmware disables AER for this RP, probably for this reason, so I did the same here
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Change subject: [NOTFORMERGE] Remaining ENV_ROMSTAGE cases
......................................................................
Patch Set 4: Code-Review-2
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Change subject: [NOTFORMERGE] Remaining ENV_ROMSTAGE cases
......................................................................
[NOTFORMERGE] Remaining ENV_ROMSTAGE cases
Change-Id: I5a1ba7ca9f5e757f062f80827d72be878e0411de
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/include/rules.h
M src/lib/cbfs.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/poppy/variants/nautilus/sku.c
M src/mainboard/google/rambi/chromeos.c
5 files changed, 12 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/63433/4
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Change subject: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT
......................................................................
[WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/util.c
M src/include/rules.h
M src/lib/cbfs.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/lippert/frontrunner-af/sema.c
M src/mainboard/pcengines/apu1/BiosCallOuts.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/soc/amd/common/pi/agesawrapper.c
M src/soc/amd/common/pi/def_callouts.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/cavium/cn81xx/sdram.c
M src/soc/mediatek/mt8186/emi.c
M src/soc/sifive/fu540/clock.c
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/i82801gx/early_init.c
M src/southbridge/intel/i82801ix/early_init.c
M src/southbridge/intel/i82801jx/early_init.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
21 files changed, 26 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/63376/5
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Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage
......................................................................
[RFC] CBMEM: Have INIT_HOOKS in every stage
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
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in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
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---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/usb/ehci_debug.c
M src/drivers/vpd/vpd.c
M src/include/cbmem.h
M src/include/rules.h
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/ext_stage_cache.c
M src/lib/fmap.c
M src/lib/imd_cbmem.c
M src/lib/program.ld
M src/lib/timestamp.c
M src/mainboard/google/gale/mmu.c
M src/mainboard/google/storm/mmu.c
M src/security/tpm/tspi/log.c
M src/security/vboot/common.c
M src/soc/amd/common/block/pm/chipset_state.c
M src/soc/amd/common/pi/heapmanager.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/broadwell/pch/power_state.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/quark/storage_test.c
M src/soc/mediatek/common/memory.c
M src/soc/qualcomm/common/qclib.c
26 files changed, 62 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63375/8
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Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
soc/amd/common/block/psp: Add platform secure boot support
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
only available with NDA customers.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
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---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
5 files changed, 223 insertions(+), 2 deletions(-)
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Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
......................................................................
cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
This patch adds a parameter wait_ap_complete in mp_callback to decide
when APs call store_callback to notify BSP it already takes jobs.
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---
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/mp.h
2 files changed, 49 insertions(+), 5 deletions(-)
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 20: Code-Review+1
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 20:
(1 comment)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/63fd0d1e_2bd43312
PS20, Line 121: d_states
d_states seems hard to understand, change to device_pwr_state?Or dev_pwr_state?
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