coreboot-gerrit May 2022

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Change in coreboot[master]: mb/starlabs/lite: Change PMC from hidden to on
by Sean Rhodes (Code Review) 05 May '22

05 May '22

Attention is currently required from: Stephen Edworthy. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63404 ) Change subject: mb/starlabs/lite: Change PMC from hidden to on ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d Gerrit-Change-Number: 63404 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Edworthy <stephen(a)starlabs.org.uk> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stephen Edworthy <stephen(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stephen Edworthy <stephen(a)starlabs.org.uk> Gerrit-Attention: Stephen Edworthy <stephen(a)starlabs.systems> Gerrit-Comment-Date: Thu, 05 May 2022 13:50:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Paul Menzel (Code Review) 05 May '22

05 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Arthur Heymans, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64077/comment/a8ba959d_a650a2c2 PS1, Line 11: Maybe add some background for the change? -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 05 May 2022 13:49:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Felix Held (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 21: (2 comments) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/8869ff16_2cf4977f PS21, Line 127: static uint32_t get_psb_status(void) would moving this function to psp_gen2.c be a good idea? that would avoid the need to have SMN_PSP_PUBLIC_BASE in psp_def.h. don't have a too strong opinion on this one though File src/soc/amd/common/block/psp/psp_def.h: https://review.coreboot.org/c/coreboot/+/60968/comment/fae82e16_d855497b PS21, Line 93: uintptr_t soc_get_psp_base_address(void); not needed any more -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 21 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 13:26:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Angel Pons (Code Review) 05 May '22

05 May '22

Attention is currently required from: Maulik V Vaghela. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > It is better to enable the SOC_INTEL_CSE_SEND_EOP_EARLY config in the board specific KConfig file to […] The problem with this is that there will be two flows to test: when SOC_INTEL_CSE_SEND_EOP_EARLY is enabled, and when it isn't. Changes could cause regressions on only one of the codepaths, so testing is more complicated. -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 05 May 2022 13:25:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64078 ) Change subject: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38 ...................................................................... soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38 Commit 198cc26e4951b3dbca588286706b7df562c45d42 (soc/amd/common/block/ psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are accessed. Since the new method doesn't need to rely on a MMIO base address to be configured, the read will always be successful and so soc_read_c2p38 doesn't need to return an error status and can directly return the value instead. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83 --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/64078/1 diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 4d860ff..d1a06fb 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -86,6 +86,6 @@ /* This command needs to be implemented by the generation specific code. */ int send_psp_command(u32 command, void *buffer); -enum cb_err soc_read_c2p38(uint32_t *msg_38_value); +uint32_t soc_read_c2p38(void); #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 820d44d..208a9bf 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -111,10 +111,9 @@ return 0; } -enum cb_err soc_read_c2p38(uint32_t *msg_38_value) +uint32_t soc_read_c2p38(void) { - *msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); - return CB_SUCCESS; + return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); } static void psp_set_spl_fuse(void *unused) @@ -122,7 +121,6 @@ if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL)) return; - uint32_t msg_38_value = 0; int cmd_status = 0; struct mbox_cmd_late_spl_buffer buffer = { .header = { @@ -130,12 +128,7 @@ } }; - if (soc_read_c2p38(&msg_38_value) != CB_SUCCESS) { - printk(BIOS_ERR, "PSP: Failed to read psp base address.\n"); - return; - } - - if (msg_38_value & CORE_2_PSP_MSG_38_FUSE_SPL) { + if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) { printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n"); cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer); psp_print_cmd_status(cmd_status, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/64078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83 Gerrit-Change-Number: 64078 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Werner Zeh (Code Review) 05 May '22

05 May '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... soc/intel/cmn/fast-spi: Add flash as reserved region Add the boot flash MMIO window to the resources to report this region as reserved to the OS. Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64077/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 19b3db7..7b736d6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -22,6 +22,8 @@ #include <spi_flash.h> #include <spi-generic.h> +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* * Get the FAST_SPIBAR. */ @@ -517,8 +519,17 @@ #endif +static void fast_spi_read_resources(struct device *dev) +{ + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add SPI boot flash as a reserved resource. */ + mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); +} + static struct device_operations fast_spi_dev_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = fast_spi_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver
by Werner Zeh (Code Review) 05 May '22

05 May '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64076 ) Change subject: src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver ...................................................................... src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver If the SPI controller is hidden from the OS (which is default on Apollo Lake) then OS has no chance to probe the device and therefore can not be aware of the resources this PCI device occupies. If the OS needs to move some resources for a reason it can happen that the new allocated window will be shadowed by the hidden PCI device resource and hence causing a conflict. As a result this MMIO window will be inaccessible from the OS which will cause issues in applications. For instance on Apollo Lake this causes flashrom to stop working. This patch adds a SSDT extension for the PCI device if it is hidden from the OS and reports the occupied resource via ACPI to the OS. Since there is no defined ACPI ID for the fast SPI controller available now, the generic one (PNP0C02) is used. Test: Boot mc_apl4 and make sure flashrom works again. Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/64076/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 9788493..19b3db7 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -2,6 +2,8 @@ #define __SIMPLE_DEVICE__ +#include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <arch/romstage.h> #include <device/mmio.h> #include <assert.h> @@ -456,10 +458,72 @@ write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); } +#if CONFIG(HAVE_ACPI_TABLES) + +/* As there is no official ACPI ID for this controller use the generic PNP ID for now. */ +static const char *fast_spi_acpi_hid(const struct device *dev) +{ + return "PNP0C02"; +} + +static const char *fast_spi_acpi_name(const struct device *dev) +{ + return "FSPI"; +} + +/* + * Generate an ACPI entry for the SPI controller. This way the allocated resources + * for the SPI controller can be communicated to the OS even if the device is + * not visible on PCI (because it is hidden) and therefore can not be probed by the OS. + */ +static void fast_spi_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *hid = fast_spi_acpi_hid(dev); + struct resource *res; + + /* Do not add SSDT if the fast SPI device is hidden. */ + if (dev->hidden || !CONFIG(SOC_INTEL_APOLLOLAKE)) + return; + if (!scope || !hid) + return; + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(fast_spi_acpi_name(dev)); + acpigen_write_name_string("_HID", hid); + acpi_device_write_uid(dev); + acpigen_write_name_string("_DDN", "ACPI Fast SPI"); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + /* Add BAR0 resource. */ + acpigen_write_mem32fixed(1, res->base, res->size); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +#endif + static struct device_operations fast_spi_dev_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = fast_spi_fill_ssdt, +#endif }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/64076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1 Gerrit-Change-Number: 64076 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver
by Werner Zeh (Code Review) 05 May '22

05 May '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64075 ) Change subject: soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver ...................................................................... soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver The fast SPI controller (usually handling the boot NOR flash) is a different controller type than the generic SPI controllers as it provides access to the boot flash and usually is not used for generic SPI slave connections. Though there is common code for the fast SPI controller it currently do not uses the PCI driver structure. This patch adds the PCI driver envelope to the fast SPI driver and moves Apollo Lake as the first platform to this driver. Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/spi/spi.c 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/64075/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 63fb68c..9788493 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -5,7 +5,9 @@ #include <arch/romstage.h> #include <device/mmio.h> #include <assert.h> +#include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> #include <commonlib/helpers.h> @@ -453,3 +455,20 @@ /* Make sure all W1C status bits get cleared. */ write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); } + +static struct device_operations fast_spi_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_APL_HWSEQ_SPI, + 0 +}; + +static const struct pci_driver fast_spi __pci_driver = { + .ops = &fast_spi_dev_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 0716e1a..256e01a 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -130,7 +130,6 @@ PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, - PCI_DID_INTEL_APL_HWSEQ_SPI, PCI_DID_INTEL_GLK_SPI0, PCI_DID_INTEL_GLK_SPI1, PCI_DID_INTEL_GLK_SPI2, -- To view, visit https://review.coreboot.org/c/coreboot/+/64075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Gerrit-Change-Number: 64075 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#13). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and with come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. devicetree based on system76/galp5. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Not working: - ACPI UCSI interface - possibly due to bug in EC FW - dTPM detection when PTT is enabled in the ME region Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 12: (2 comments) File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/f436bfc8_39689356 PS1, Line 58: register "LpmStateDisableMask" = " : LPM_S0i2_1 | : LPM_S0i2_2 | : LPM_S0i3_1 | : LPM_S0i3_2 | : LPM_S0i3_3 | : LPM_S0i3_4 : > Why does s0i2. […] Vendor firmware does this, I assumed there was a reason for it, but maybe there isn't? :D File src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb: PS3: > Are any PCIe RPs wired to a slot? Yes, one CPU RP wired to SSD slot and one PCH RP wired to WiFi card slot -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 12:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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