coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Aamir Bohra, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60968 to look at the new patch set (#22). Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... soc/amd/common/block/psp: Add platform secure boot support Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is only available with NDA customers. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc A src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 5 files changed, 226 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60968/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 22 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/lib: add interactive debug shell
by Name of user not set (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1003801, Fred Reitberger, Julian Schroeder, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Julian Schroeder, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63871 to look at the new patch set (#2). Change subject: src/lib: add interactive debug shell ...................................................................... src/lib: add interactive debug shell Rationale for debug shell for coreboot: -stop system at various locations to preserve state (Smart Trace Buffer) -abililty to probe system state interactively, i.e. communicate with service processors, call specific functions -quicker reboot cycles: no need to boot into payload or OS -ability to add tests: one build, multiple experiments can be run interactively -adding additonal test is simple. -equivalent of 'BIOS Settings' can be added -get boot time information (cbmem -t style) when serial console out is disabled This has been tested on AMD Cezanne and AMD Sabine. Change-Id: Idc06dcbe5e58864abc9d7ec05c9972d2abc9f458 Signed-off-by: JulianMarcusSchroeder <julianmarcusschroeder(a)gmail.com> --- A Documentation/debug/debug_shell.md M Documentation/index.md M src/Kconfig A src/include/console/debug_shell.h M src/include/timestamp.h M src/lib/Makefile.inc A src/lib/debug_shell.c A src/lib/dhrystone.c M src/lib/timestamp.c M src/soc/amd/common/Kconfig.common M src/soc/amd/common/Makefile.inc M src/soc/amd/common/block/smu/Makefile.inc A src/soc/amd/common/debug/Kconfig A src/soc/amd/common/debug/Makefile.inc A src/soc/amd/common/debug/soc_debug_commands.c 15 files changed, 1,586 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/63871/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc06dcbe5e58864abc9d7ec05c9972d2abc9f458 Gerrit-Change-Number: 63871 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63954 ) Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done ...................................................................... soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done This patch calls into the PMC IPC function that informs about PMC enumeration. Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC IPC, hence, this patch is considered as an improvement over FSP Notify Phase API. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS without any PMC IPC error. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index d926dbb..c291e34 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -9,6 +9,7 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pcr_ids.h> #include <soc/pm.h> @@ -36,6 +37,9 @@ setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | PM_CFG_XRAM_READ_DISABLE); } + + /* Send PMC IPC to inform about PCI enumeration done */ + pmc_send_pci_enum_done(); } static void pch_lockdown_cfg(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/63954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2 Gerrit-Change-Number: 63954 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63953 ) Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done ...................................................................... soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done This patch sends an IPC to PMC to inform about PCI enumeration. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I77d428f9501feaccab8bb431090d10ce8d3af9b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fc65a08..62f27a9 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -28,6 +28,9 @@ */ enum pch_pmc_xtal pmc_get_xtal_freq(void); +/* pmc_send_pci_enum_done() - send PMC IPC to inform PCI enumeration is done. */ +void pmc_send_pci_enum_done(void); + /* Forward declare the power state struct here */ struct chipset_power_state; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index a733920..0f1da72 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -10,6 +10,7 @@ #include <cpu/x86/smm.h> #include <console/console.h> #include <halt.h> +#include <intelblocks/pmc_ipc.h> #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> #include <intelblocks/tco.h> @@ -21,6 +22,9 @@ #include <string.h> #include <timer.h> +#define PMC_IPC_BIOS_RST_COMPLETE 0xd0 +#define PMC_IPC_BIOS_RST_SUBID_PCI_ENUM_DONE 0 + static struct chipset_power_state power_state; /* List of Minimum Assertion durations in microseconds */ @@ -785,3 +789,15 @@ return XTAL_UNKNOWN_FREQ; } } + +void pmc_send_pci_enum_done(void) +{ + struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer rsp; + uint32_t cmd; + + cmd = pmc_make_ipc_cmd(PMC_IPC_BIOS_RST_COMPLETE, + PMC_IPC_BIOS_RST_SUBID_PCI_ENUM_DONE, 0); + if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) + printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77d428f9501feaccab8bb431090d10ce8d3af9b2 Gerrit-Change-Number: 63953 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Use wait_finished_mp_run_on_all_cpus for APs MTRR init
by Arthur Heymans (Code Review) 05 May '22

05 May '22

Attention is currently required from: Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63567 ) Change subject: soc/intel/common: Use wait_finished_mp_run_on_all_cpus for APs MTRR init ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26 Gerrit-Change-Number: 63567 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:20:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/crota: setting for codec reset pin
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64027 ) Change subject: mb/google/brya/var/crota: setting for codec reset pin ...................................................................... mb/google/brya/var/crota: setting for codec reset pin Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/crota/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index a546455..35803a0 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -22,8 +22,8 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + /* B15 : PROC_GP3 ==> AUD_RST_L */ + PAD_CFG_GPO(GPP_B15, 1, PWROK), /* C3 : GPP_C3 ==> SML0_SMBCLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/64027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Gerrit-Change-Number: 64027 Gerrit-PatchSet: 4 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Return ACPI_S4 as previous sleep state
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64002 ) Change subject: soc/intel: Return ACPI_S4 as previous sleep state ...................................................................... soc/intel: Return ACPI_S4 as previous sleep state pmc_prev_sleep_state() isn't handling the case where acpi_sleep_from_pm1() returns ACPI_S4. Pass that value along so it can get set as a prev_sleep_state. Without this, consumers see prev_sleep_state as 0 and always treat resume as a cold boot. With this, consumers can correctly do behavior specific to S4 resume, like skipping the disconnect IPC command to the PMC on Alderlake systems. BUG=b:230031158 TEST=Resume from S4 on Primus4es Signed-off-by: Evan Green <evgreen(a)chromium.org> Change-Id: I3fb3dc428a749db80293e51a04a2096514a7b689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index a2e3e9e..a733920 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -399,6 +399,9 @@ if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; + case ACPI_S4: + prev_sleep_state = ACPI_S4; + break; case ACPI_S5: prev_sleep_state = ACPI_S5; break; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/64002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fb3dc428a749db80293e51a04a2096514a7b689 Gerrit-Change-Number: 64002 Gerrit-PatchSet: 4 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Arthur Heymans (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 7: (1 comment) File src/include/cpu/x86/mp.h: https://review.coreboot.org/c/coreboot/+/63566/comment/6e0db795_c64d4e27 PS2, Line 109: /* : * This function is similar to mp_run_on_aps but the BSP will wait for all APs : * to complete the assigned tasks and continue : */ : enum cb_err mp_run_on_aps_and_wait_for_complete(void (*func)(void *), void *arg, : int logical_cpu_num, long expire_us); > yes, thanks for reminding. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 14:20:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Arthur Heymans (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 7: Code-Review+2 (2 comments) Patchset: PS7: Looks good. File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63566/comment/e5a7d0d0_684f81cf PS2, Line 972: store_callback > Hi Tim, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 14:19:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Fix SD card power sequence
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64023 ) Change subject: mb/google/skyrim: Fix SD card power sequence ...................................................................... mb/google/skyrim: Fix SD card power sequence Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 53c40de..41d6bbe 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -195,6 +195,8 @@ PAD_GPO(GPIO_7, HIGH), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* SD_AUX_RESET_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), }; __weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/64023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422 Gerrit-Change-Number: 64023 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit May 2022