coreboot-gerrit May 2022

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Change in coreboot[master]: soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver
by Subrata Banik (Code Review) 05 May '22

05 May '22

Attention is currently required from: Nico Huber, Arthur Heymans, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64075 ) Change subject: soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @werner, are you planning to lift all FAST SPI device ids later in to common fast_spi code as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/64075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Gerrit-Change-Number: 64075 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 05 May 2022 16:09:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Subrata Banik (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Kane Chen, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 7: (2 comments) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63566/comment/15db83ae_f2aac574 PS7, Line 864: tab? https://review.coreboot.org/c/coreboot/+/63566/comment/8fb36ba7_79b5086b PS7, Line 1049: wait_finished_mp_run_on_all_cpus nit: `mp_run_on_all_cpus_with_delay` to maintain the naming alignment as `mp_run_on_all_xxx`? -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 16:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63652 ) Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR ...................................................................... mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects EC of I2C 5 bus and GPIO D22, D23, as well as, SoC of GPIO E11, refer to mainboard schematic. BUG=b:213549229 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: If172d13aa62503547227adf91f049ea50b948888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 2 files changed, 77 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c index 57573cc..2af138d 100644 --- a/src/mainboard/google/dedede/variants/beadrix/gpio.c +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -21,6 +21,8 @@ PAD_NC(GPP_C19, NONE), /* C22 : UART2_RTS_N ==> NC */ PAD_NC(GPP_C22, NONE), + /* C23 : UART2_CTS_N ==> NC */ + PAD_NC(GPP_C23, NONE), /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ PAD_CFG_GPO(GPP_D0, 1, DEEP), @@ -38,6 +40,10 @@ PAD_NC(GPP_D20, NONE), /* D21 : WWAN_WLAN_COEX3 ==> TP */ PAD_NC(GPP_D21, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* D23 : AP_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E1 : EMR_RESET_L ==> NC */ PAD_NC(GPP_E1, NONE), @@ -47,6 +53,8 @@ PAD_NC(GPP_E5, NONE), /* E10 : GPP_E10/SML_DATA0 ==> NC */ PAD_NC(GPP_E10, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE), /* G0 : SD_CMD ==> NC */ PAD_NC(GPP_G0, NONE), diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index f3f5d56..2c82fa5 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -14,10 +14,11 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | | #| I2C2 | Touchscreen | - #| I2C3 | Camera | + #| I2C3 | | #| I2C4 | Audio | + #| I2C5 | P-sensor | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -39,6 +40,18 @@ .i2c[4] = { .speed = I2C_SPEED_FAST, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, }" device domain 0 on @@ -131,6 +144,60 @@ device i2c 1a on end end end # I2C 4 + device pci 19.1 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "uid" = "0" + register "reg_gnrl_ctrl0" = "0x0a" + register "reg_gnrl_ctrl1" = "0x22" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_afe_ph0" = "0x37" + register "reg_afe_ph1" = "0x29" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x2d" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x40" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x6f" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + device i2c 28 on end + end + end # I2C 5 device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1 device pci 1f.3 on -- To view, visit https://review.coreboot.org/c/coreboot/+/63652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If172d13aa62503547227adf91f049ea50b948888 Gerrit-Change-Number: 63652 Gerrit-PatchSet: 10 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Super Ni <super.ni(a)intel.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshihau(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Jack Cheng <jack.cheng(a)ecs.corp-partner.google.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google: Notify DPTF driver power participant on PD event
by Tim Wawrzynczak (Code Review) 05 May '22

05 May '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Rizwan Qureshi. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62946 ) Change subject: ec/google: Notify DPTF driver power participant on PD event ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62946/comment/f0c859fd_c1fdda88 PS11, Line 8: : The DPTF power participant device needs to be notified when : power source changes so it can re-evaluate power source and : power source change count, this can be later used by DPTF along : with methods provided by EC. What policy uses this notification? File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/62946/comment/a23d3039_3e924a36 PS11, Line 87: PBOK, 8, // Power source change count from dptf where is the corresponding change in the EC code? -- To view, visit https://review.coreboot.org/c/coreboot/+/62946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Gerrit-Change-Number: 62946 Gerrit-PatchSet: 11 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Thu, 05 May 2022 16:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/memory_info.h: Increase DIMM_INFO_TOTAL to 32
by Johnny Lin (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Marc Jones, Patrick Rudolph, Jonathan Zhang, Paul Menzel, Angel Pons, lichenchen.carl, Nill Ge, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64041 ) Change subject: include/memory_info.h: Increase DIMM_INFO_TOTAL to 32 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64041/comment/ad686fd6_99fd519c PS3, Line 11: > Tested how? On certain 2-socket board that has more than 16 DIMMs can verify the increased number of SMBIOS type 17 tables are created. -- To view, visit https://review.coreboot.org/c/coreboot/+/64041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If72a8622ac1e7e67646aa4dd24b99637fb8b1297 Gerrit-Change-Number: 64041 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:56:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/amdfwtool: Add IKEK key for Trusted Application
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64040 ) Change subject: util/amdfwtool: Add IKEK key for Trusted Application ...................................................................... util/amdfwtool: Add IKEK key for Trusted Application This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3273b72..c58d1e9 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -265,6 +265,7 @@ { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index cc0a3b1..0bef43a 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -58,6 +58,7 @@ AMD_FW_SPIROM_CFG = 0x5c, AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, + AMD_TA_IKEK = 0x8d, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index a080eec..14c15673 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -328,6 +328,9 @@ } else { fw_type = AMD_FW_SKIP; } + } else if (strcmp(fw_name, "TA_IKEK_FILE") == 0) { + fw_type = AMD_TA_IKEK; + subprog = 0; } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Gerrit-Change-Number: 64040 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Mohan Viswanathan Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Add enum for `DdiPortXConfig`
by Tim Crawford (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Jeremy Soller, Nick Vaccaro, Angel Pons, Michael Niewöhner. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64047 ) Change subject: soc/intel/tigerlake: Add enum for `DdiPortXConfig` ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Gerrit-Change-Number: 64047 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 14:47:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: add interactive debug shell
by Paul Menzel (Code Review) 05 May '22

05 May '22

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Change in coreboot[master]: src/lib: add interactive debug shell
by Paul Menzel (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Stefan Reinauer, Name of user not set #1003801, Fred Reitberger, Julian Schroeder, ron minnich, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63871 ) Change subject: src/lib: add interactive debug shell ...................................................................... Patch Set 2: (13 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63871/comment/10484b32_903a17b4 PS2, Line 2: JulianMarcusSchroeder Please add spaces. https://review.coreboot.org/c/coreboot/+/63871/comment/1021ce6d_f37bc83e PS2, Line 11: -stop Please add a space. https://review.coreboot.org/c/coreboot/+/63871/comment/5dd51cc1_70785cb7 PS2, Line 14: -quicker reboot cycles: no need to boot into payload or OS Booting the payload shouldn’t make a lot of difference as quick as coreboot is. (Well below one second?) https://review.coreboot.org/c/coreboot/+/63871/comment/fc288a0c_058811b3 PS2, Line 15: -ability to add tests: one build, multiple experiments can be run interactively Please elaborate. https://review.coreboot.org/c/coreboot/+/63871/comment/342e4005_b37d1e96 PS2, Line 11: -stop system at various locations to preserve state (Smart Trace Buffer) : -abililty to probe system state interactively, i.e. communicate with service : processors, call specific functions : -quicker reboot cycles: no need to boot into payload or OS : -ability to add tests: one build, multiple experiments can be run interactively : -adding additonal test is simple. : -equivalent of 'BIOS Settings' can be added : -get boot time information (cbmem -t style) when serial console out is disabled Please reflow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/63871/comment/7a28d813_29abcc82 PS2, Line 23: JulianMarcusSchroeder Ditto. Patchset: PS2: Very nice, but no idea, if that aligns with coreboot’s philosophy. A lot of the use cases would also be solved by a separate payload. File Documentation/debug/debug_shell.md: https://review.coreboot.org/c/coreboot/+/63871/comment/f535a6ec_d2c5495d PS2, Line 1: #Debugging Please add spaces. Also below. https://review.coreboot.org/c/coreboot/+/63871/comment/52eb9906_03901b41 PS2, Line 5: If one wants to benchmark a system's boot time up to the payload level, : there is no need to boot all the way to the OS. : If a system exhibits issues before reaching the payload level GDB or an : external debugger might be needed which isn't always practical or convenient. : Sometimes relevant system state is lost further into the boot process. : In addition, calling coreboot functions and utilities is easiest done within : coreboot. Please reflow. (Also below.) https://review.coreboot.org/c/coreboot/+/63871/comment/529307e0_c5e72f4a PS2, Line 28: Maybe add one example with QEMU? File src/Kconfig: https://review.coreboot.org/c/coreboot/+/63871/comment/2b033957_0c435a93 PS2, Line 890: amd and https://review.coreboot.org/c/coreboot/+/63871/comment/10dabd8b_501ca29c PS2, Line 891: A An https://review.coreboot.org/c/coreboot/+/63871/comment/0f7aae52_981f68c0 PS2, Line 892: a an -- To view, visit https://review.coreboot.org/c/coreboot/+/63871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc06dcbe5e58864abc9d7ec05c9972d2abc9f458 Gerrit-Change-Number: 63871 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 05 May 2022 14:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GPU power sequencing
by Tim Wawrzynczak (Code Review) 05 May '22

05 May '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62384 ) Change subject: mb/google/brya/var/agah: Add GPU power sequencing ...................................................................... mb/google/brya/var/agah: Add GPU power sequencing This patch adds support for power sequencing of the Nvidia GN3050 for agah, which uses PCH GPIOs to control the 5 power rails required for the GPU. The GPU is power sequenced on during mainboard initialization, then it is enumerated on the PCI bus and its resources are assigned. This GPU will be used in a sort of "hybrid graphics" mode, therefore during finalization, since its PCI BARs are saved into ACPI memory and the GPU is not required upon initial boot, the GPU is power sequenced off. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/agah/Makefile.inc M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/agah/overridetree.cb A src/mainboard/google/brya/variants/agah/variant.c 4 files changed, 191 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/agah/Makefile.inc b/src/mainboard/google/brya/variants/agah/Makefile.inc index 139345f..3d5212f 100644 --- a/src/mainboard/google/brya/variants/agah/Makefile.inc +++ b/src/mainboard/google/brya/variants/agah/Makefile.inc @@ -6,3 +6,4 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 81c9724..369e373 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -75,8 +75,8 @@ /* D16 : ISH_UART0_CTS# ==> NC */ PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), - /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_OD */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index ad23f7b..70bc092 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -58,6 +58,15 @@ }" device domain 0 on + device ref pcie4_0 on + # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 alias dgpu on end + end device ref dtt on chip drivers/intel/dptf ## sensor information diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c new file mode 100644 index 0000000..979e4e0 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> +#include <timer.h> +#include <types.h> + +#define GPU_1V8_PWR_EN GPP_E18 +#define GPU_1V8_PG GPP_E20 +#define NV33_PWR_EN GPP_A21 +#define NV33_PG GPP_A22 +#define NVVDD_PWR_EN GPP_E0 +#define NVVDD_PG GPP_E16 +#define PEXVDD_PWR_EN GPP_E10 +#define PEXVDD_PG GPP_E17 +#define FBVDD_PWR_EN GPP_A17 +#define FBVDD_PG GPP_E4 +#define GPU_PERST_L GPP_B3 +#define GPU_ALLRAILS_PG GPP_E5 + +#define DEFAULT_PG_TIMEOUT_US 20000 + +#define VGAR_BYTE_OFFSET 5 + +/* Maximum size of PCI config space to save. */ +#define GPU_CONFIG_SAVE_SPACE_BYTES 0x100 + +static bool gpu_powered_on; + +struct power_rail_sequence { + const char *name; + + /* This is the GPIO (output) connected to the VR's enable pin. */ + gpio_t pwr_en_gpio; + bool pwr_en_active_low; + + /* This is the GPIO (input) connected to the VR's power-good pin. */ + gpio_t pg_gpio; +}; + +/* In GCOFF exit order (i.e., power-on order) */ +static const struct power_rail_sequence gpu_rails[] = { + { "GPU 1.8V", GPU_1V8_PWR_EN, false, GPU_1V8_PG, }, + { "NV3_3", NV33_PWR_EN, false, NV33_PG, }, + { "NVVDD+MSVDD", NVVDD_PWR_EN, true, NVVDD_PG, }, + { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, }, + { "FBVDD", FBVDD_PWR_EN, false, FBVDD_PG, }, +}; + +enum rail_state { + RAIL_OFF = 0, + RAIL_ON = 1, +}; + +/* Assert the VR's enable pin, and wait until the VR's power-good is asserted. */ +static bool sequence_rail(const struct power_rail_sequence *seq, enum rail_state state) +{ + if (seq->pwr_en_active_low) + state = !state; + + gpio_output(seq->pwr_en_gpio, state); + return wait_us(DEFAULT_PG_TIMEOUT_US, gpio_get(seq->pg_gpio) == state) > 0; +} + +static void dgpu_power_sequence_off(void) +{ + /* Assert reset and clear power-good */ + gpio_output(GPU_PERST_L, 0); + mdelay(5); + + /* Inform the GPU that the power is no longer good. */ + gpio_output(GPU_ALLRAILS_PG, 0); + + for (int i = (int)ARRAY_SIZE(gpu_rails) - 1; i >= 0; i--) { + if (!sequence_rail(&gpu_rails[i], RAIL_OFF)) { + printk(BIOS_ERR, "Failed to disable %s rail, continuing!\n", + gpu_rails[i].name); + } + } +} + +static void dgpu_power_sequence_on(void) +{ + /* Assert PERST# */ + gpio_output(GPU_PERST_L, 0); + + for (size_t i = 0; i < ARRAY_SIZE(gpu_rails); i++) { + if (!sequence_rail(&gpu_rails[i], RAIL_ON)) { + printk(BIOS_ERR, "Failed to enable %s rail, sequencing back down!\n", + gpu_rails[i].name); + + /* If an error occurred, then perform the power-off sequence and + return early to avoid setting GPU_ALLRAILS_PG and PERST_L. */ + dgpu_power_sequence_off(); + return; + } + } + + /* Set power-good and release PERST# */ + gpio_output(GPU_ALLRAILS_PG, 1); + mdelay(1); + gpio_output(GPU_PERST_L, 1); + + printk(BIOS_INFO, "Sequenced GPU successfully\n"); + gpu_powered_on = true; +} + +void variant_init(void) +{ + if (acpi_is_wakeup_s3()) + return; + + dgpu_power_sequence_on(); +} + +void variant_finalize(void) +{ + if (acpi_is_wakeup_s3() || !gpu_powered_on) + return; + + /* + * Because the dGPU is used here in a way similar to "hybrid graphics" + * modes, it is powered down here. The DRIVERS_GFX_NVIDIA_SAVE_BARS + * option is selected for agah, so the BARs will be saved to ACPI memory + * during its finalize routine. Thus, it is powered down here, as the + * proper resources have already been allocated. + */ + dgpu_power_sequence_off(); + + printk(BIOS_INFO, "GPU power sequenced off.\n"); +} + +/* Save PCI BARs to the ACPI copy of the "saved PCI config space" */ +void variant_fill_ssdt(const struct device *unused) +{ + if (!gpu_powered_on) + return; + + const struct device *dgpu = DEV_PTR(dgpu); + acpigen_write_scope("\\_SB.PCI0.PEG0.PEGP"); + acpigen_write_method("_INI", 0); + { + /* Local0 = VGAR */ + acpigen_write_store(); + acpigen_emit_namestring("VGAR"); + acpigen_emit_byte(LOCAL0_OP); + + /* + * CreateDWordField(Local0, 11, BAR0) + * BAR0 = bases[0] + * CreateDWordField(Local0, 15, BAR1) + * BAR1 = bases[1] + * ... + */ + for (unsigned int idx = PCI_BASE_ADDRESS_0, i = 0; idx <= PCI_BASE_ADDRESS_5; + idx += sizeof(uint32_t), ++i) { + char name[ACPI_NAME_BUFFER_SIZE]; + const struct resource *res; + + res = probe_resource(dgpu, idx); + if (!res) + continue; + + snprintf(name, sizeof(name), "BAR%1d", i); + acpigen_write_create_dword_field(LOCAL0_OP, idx - VGAR_BYTE_OFFSET, + name); + acpigen_write_store_int_to_namestr(res->base & 0xffffffff, name); + } + + /* VGAR = Local0 */ + acpigen_write_store_op_to_namestr(LOCAL0_OP, "VGAR"); + } + + acpigen_write_method_end(); + acpigen_write_scope_end(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Gerrit-Change-Number: 62384 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2022