coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

1 participants
6166 discussions

Change in coreboot[master]: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63924 ) Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K ...................................................................... soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K The per-file hash for CBFS_VERIFICATION, stored as a CBFS file attribute, would increase the total RO metadata size by 75% (3796->6656 for corsola). Therefore, in order to make RO metadata cache fit into CBFS_MCACHE, enlarge it from 8K to 16K. Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K (only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also shuffle the regions in SRAM with better comments. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel BRANCH=none Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 22 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index 942c919..1764632 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -21,33 +21,39 @@ SECTIONS { + /* MT8186 has 64KB SRAM in total. */ SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) - TTB(0x00103000, 28K) - DMA_COHERENT(0x0010A000, 4K) - TPM_TCPA_LOG(0x0010B000, 2K) - FMAP_CACHE(0x0010B800, 2K) - WATCHDOG_TOMBSTONE(0x0010C000, 4) - CBFS_MCACHE(0x0010C004, 8K - 4) - STACK(0x0010E000, 7K) - TIMESTAMP(0x0010FC00, 1K) - /* MT8186 has 64KB SRAM. */ + /* Regions that need to stay in SRAM. */ + TTB(0x00100000, 28K) + DMA_COHERENT(0x00107000, 4K) + STACK(0x00108000, 10K) + WATCHDOG_TOMBSTONE(0x0010a800, 4) + /* EMPTY(0x0010a804, 1K - 4) */ + /* Regions that can also be moved to SRAM_L2C. */ + TIMESTAMP(0x0010ac00, 1K) + TPM_TCPA_LOG(0x0010b000, 2K) + FMAP_CACHE(0x0010b800, 2K) + CBFS_MCACHE(0x0010c000, 16K) SRAM_END(0x00110000) /* - * The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM - * has configured only half of L2/L3 cache as SRAM and the rest for cache - * so we can't use them unless if we disable L2C and reconfigure (be aware - * we can't configure whole L3 to SRAM without any cache). + * The L3 (can be used as SRAM_L2C) is 1MB in total. However the bootROM has configured + * only half of L2/L3 cache as SRAM and the rest for cache so we can't use them unless + * if we disable L2C and reconfigure (be aware we can't configure whole L3 to SRAM + * without any cache). */ SRAM_L2C_START(0x00200000) - /* 4K reserved for BOOTROM until BOOTBLOCK is started */ + /* + * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address + * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started. + */ BOOTBLOCK(0x00201000, 60K) /* * The needed size can be obtained by: * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ - DRAM_INIT_CODE(0x00210000, 196K) + DRAM_INIT_CODE(0x00210000, 184K) + VBOOT2_WORK(0x0023e000, 12K) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K) PRERAM_CBFS_CACHE(0x00264000, 48K) PRERAM_CBMEM_CONSOLE(0x00270000, 64K) -- To view, visit https://review.coreboot.org/c/coreboot/+/63924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5 Gerrit-Change-Number: 63924 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63925 ) Change subject: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION ...................................................................... cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION MediaTek's bootROM expects a SHA256 of the bootblock data at the end of bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need to re-generate the hash whenever a file is added to or removed from CBFS. BUG=b:229670703 TEST=sudo emerge coreboot-utils TEST=emerge-corsola coreboot chromeos-bootimage TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/cbfstool/platform_fixups.c 1 file changed, 96 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c index ea2d316..b2e12cf 100644 --- a/util/cbfstool/platform_fixups.c +++ b/util/cbfstool/platform_fixups.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/endian.h> +#include <string.h> + #include "cbfs.h" #include "cbfs_sections.h" #include "elfparsing.h" @@ -105,12 +108,105 @@ return 0; } +/* + * MediaTek bootblock.bin layout (see util/mtkheader/gen-bl-img.py): + * header 2048 bytes + * gfh info 176 bytes, where bytes 32-35 (in little endian) is the + * total size excluding the header (gfh info + data + hash) + * data `data_size` bytes + * hash 32 bytes, SHA256 of "gfh info + data" + * padding + */ +#define MEDIATEK_BOOTBLOCK_HEADER_SIZE 2048 +#define MEDIATEK_BOOTBLOCK_GFH_SIZE 176 +static void *mediatek_find_hash(struct buffer *bootblock, struct vb2_hash *real_hash) +{ + struct buffer buffer; + size_t data_size; + const char emmc_magic[] = "EMMC_BOOT"; + const char sf_magic[] = "SF_BOOT"; + const char brlyt_magic[] = "BRLYT"; + const size_t brlyt_offset = 512; + + buffer_clone(&buffer, bootblock); + + /* Doesn't seem to be MediaTek image */ + if (buffer_size(&buffer) < + MEDIATEK_BOOTBLOCK_HEADER_SIZE + MEDIATEK_BOOTBLOCK_GFH_SIZE) + return NULL; + + /* Check header magic */ + if (!buffer_check_magic(&buffer, emmc_magic, strlen(emmc_magic)) && + !buffer_check_magic(&buffer, sf_magic, strlen(sf_magic))) + return NULL; + + /* Check "BRLYT" */ + buffer_seek(&buffer, brlyt_offset); + if (!buffer_check_magic(&buffer, brlyt_magic, strlen(brlyt_magic))) + return NULL; + + buffer_seek(&buffer, MEDIATEK_BOOTBLOCK_HEADER_SIZE - brlyt_offset); + data_size = read_le32(buffer_get(&buffer) + 32); + if (data_size <= MEDIATEK_BOOTBLOCK_GFH_SIZE + VB2_SHA256_DIGEST_SIZE) { + ERROR("fixups: MediaTek: data size too small: %zu\n", data_size); + return NULL; + } + data_size -= MEDIATEK_BOOTBLOCK_GFH_SIZE + VB2_SHA256_DIGEST_SIZE; + + if (buffer_size(&buffer) < + MEDIATEK_BOOTBLOCK_GFH_SIZE + data_size + VB2_SHA256_DIGEST_SIZE) { + ERROR("fixups: MediaTek: not enough data: %zu\n", buffer_size(&buffer)); + return NULL; + } + + if (vb2_hash_calculate(buffer_get(&buffer), + MEDIATEK_BOOTBLOCK_GFH_SIZE + data_size, + VB2_HASH_SHA256, real_hash)) { + ERROR("fixups: MediaTek: vboot digest error\n"); + return NULL; + } + + buffer_seek(&buffer, MEDIATEK_BOOTBLOCK_GFH_SIZE + data_size); + return buffer_get(&buffer); +} + +static bool mediatek_probe(struct buffer *buffer) +{ + struct vb2_hash real_hash; + void *hash = mediatek_find_hash(buffer, &real_hash); + if (!hash) + return false; + + if (memcmp(real_hash.raw, hash, VB2_SHA256_DIGEST_SIZE)) { + ERROR("fixups: Found MediaTek bootblock, but existing hash doesn't match!\n"); + return false; + } + + return true; +} + +static int mediatek_fixup(struct buffer *buffer, unused size_t offset) +{ + struct vb2_hash real_hash; + void *hash = mediatek_find_hash(buffer, &real_hash); + if (!hash) { + ERROR("fixups: Cannot find MediaTek header anymore!\n"); + return -1; + } + + memcpy(hash, real_hash.raw, VB2_SHA256_DIGEST_SIZE); + INFO("fixups: Updated MediaTek bootblock hash.\n"); + return 0; +} + platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, const char *region_name) { if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK)) { if (qualcomm_probe(buffer, offset)) return qualcomm_fixup; + else if (mediatek_probe(buffer)) + return mediatek_fixup; } else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS)) { /* TODO: add fixups for primary CBFS bootblock platforms, if needed */ } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/63925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830 Gerrit-Change-Number: 63925 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 13: (3 comments) File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/bbf316b2_8ed2e8cb PS6, Line 115: device ref peg on > Add "smbios_slot_desc"? Added https://review.coreboot.org/c/coreboot/+/62498/comment/798eae64_0faac8b2 PS6, Line 308: register "PcieRpEnable[10]" = "1" > register "PcieRpSlotImplemented[10]" = "1" […] Added and added File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/a5dab4f2_4a45d31b PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ : > configured in gpio_early Right, removed them from `gpio.c` altogether. -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 14:16:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#14). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and with come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. devicetree based on system76/galp5. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Not working: - ACPI UCSI interface - possibly due to bug in EC FW - dTPM detection when PTT is enabled in the ME region Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Kane Chen (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Tim Wawrzynczak. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 7: (3 comments) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63566/comment/7fe2d921_61410720 PS5, Line 932: if (atomic_read(&ap_busy[i]) == -1) : cpus_finish++; > > Instead of using 0/1 for busy/not busy, this patchset use 1 and -1 to indicate busy/not busy becau […] i init the array with AP_NOT_BUSY in the beginning of ap_wait_for_instruction and it's after mp_init. Hopefully, it's acceptable because it's more clear where the array should be init https://review.coreboot.org/c/coreboot/+/63566/comment/5690c3bb_19c7b254 PS5, Line 977: atomic_set(&ap_busy[cur_cpu], 1); > Probably best to add a comment that this needs to happen before storing NULL to the callback as the […] done https://review.coreboot.org/c/coreboot/+/63566/comment/613775e0_ead42227 PS5, Line 985: goto finish; > Reverse the if condition and avoid goto. done -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 05 May 2022 14:15:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Kane Chen (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63566 to look at the new patch set (#7). Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus This patch adds a parameter wait_ap_complete in mp_callback to decide when APs call store_callback to notify BSP it already takes jobs. This can allow the caller to decide whether it should wait all APs to continue or not. Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/include/cpu/x86/mp.h 2 files changed, 61 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63566/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Felix Held (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 21: (1 comment) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/a0572645_85c70e52 PS21, Line 127: static uint32_t get_psb_status(void) > No, want to keep psb specific function get_psb_status() in psb specific file itself. ok -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 21 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/acpi: Refactor to reduce code duplication, use named constants
by Lean Sheng Tan (Code Review) 05 May '22

05 May '22

Attention is currently required from: Abel Briggs. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64012 ) Change subject: ec/acpi: Refactor to reduce code duplication, use named constants ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: has this been tested with any hardware? -- To view, visit https://review.coreboot.org/c/coreboot/+/64012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda5c030ff81f1046be58aa1fcafdcf71a27cd41 Gerrit-Change-Number: 64012 Gerrit-PatchSet: 2 Gerrit-Owner: Abel Briggs <abelbriggs1(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Abel Briggs <abelbriggs1(a)hotmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38
by Felix Held (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64078 ) Change subject: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38 ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/64078/comment/a7c5a1b4_e1d70a64 PS1, Line 116: SMN_PSP_PUBLIC_BASE > can this be defined in header file, as this base address will be needed for other smn offset access […] that change is unrelated to this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/64078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83 Gerrit-Change-Number: 64078 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:04:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Felix Held (Code Review) 05 May '22

05 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 21: (1 comment) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/22857174_3c73c240 PS21, Line 154: if (soc_read_c2p38(&status)) { https://review.coreboot.org/c/coreboot/+/64078 changes the function signature -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 21 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 14:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2022