coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#12). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and with come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. Original devicetree based on system76/galp5. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Not working: - ACPI UCSI interface - possibly due to bug in EC FW - dTPM detection when PTT is enabled in the ME region Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Sridhar Siricilla (Code Review) 05 May '22

05 May '22

Attention is currently required from: Maulik V Vaghela. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > @Sridhar, can u please comment ? It is better to enable the SOC_INTEL_CSE_SEND_EOP_EARLY config in the board specific KConfig file to avoid the conflicts with other designs. -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 05 May 2022 12:32:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62498/comment/96713436_e646ed9f PS6, Line 8: > Are there any known problems? Added a status to the commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 12:10:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#11). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Not working: - ACPI UCSI interface - possibly due to bug in EC FW - dTPM detection when PTT is enabled in the ME region Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michael Niewöhner. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 9: (1 comment) File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/5d0ee13f_8c1ea7e6 PS6, Line 17: register "external_bypass" = "1" > I expected that :D same on other devices... […] Oh, alright, removed! -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 12:01:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#10). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Kopeć (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62498 to look at the new patch set (#9). Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME). These laptops have an Intel TigerLake-U processor and an ITE IT5570E embedded controller, and come optional NVIDIA Optimus hybrid graphics depending on model. `x` in device name indicates chassis color. Working: - Booting UEFI OS via TianoCore payload from MrChromebox's fork - All hotkeys - except Touchpad Toggle, which requires tweak in OS - s0ix / modern standby, including when a USB-C is device connected - Onboard discrete TPM 2.0 - USB-A and USB-C ports including TBT, HDMI, SD card, audio - Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl M src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.asl A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c 14 files changed, 783 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Arthur Heymans (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 5: (3 comments) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63566/comment/d2ecce6b_c465b4cb PS5, Line 932: if (atomic_read(&ap_busy[i]) == -1) : cpus_finish++; > Instead of using 0/1 for busy/not busy, this patchset use 1 and -1 to indicate busy/not busy because of the below reason. > > size of ap_busy array is CONFIG_MAX_CPUS > however the actual running cpu could be less than CONFIG_MAX_CPUS > That means when all AP takes the jobs, some elements of ap_busy are always 0 since actual running cpu could be less than CONFIG_MAX_CPUS > ex: > Assume we have 4 cpus, and CONFIG_MAX_CPUS = 8 > when APs take jobs, ap_busy is like [1,1,1,1,0,0,0,0] > when APs finishes all the task, ap_busy is like [0,0,0,0,0,0,0,0] > the last four elements is always 0 since the dut doesn't have that many CPUs. > > in this case cpus_finish will be 8 and never equal to global_num_aps (4 in this case) > This is why i can't simply use 0/1 to judge it's busy/not busy. > > hope this explains. This has the problem that you needs to initialize all the ap_busy variables before you can successfully use the ap_busy variables in wait_ap_finish. Can you just initialize them to not busy after the MP init. If a CPU does not exist the busy bit will never be set on those. Also best to use an enum over raw numbers. https://review.coreboot.org/c/coreboot/+/63566/comment/56ab2890_d55c5863 PS5, Line 977: atomic_set(&ap_busy[cur_cpu], 1); Probably best to add a comment that this needs to happen before storing NULL to the callback as the busy bit is checked later by the BSP (to avoid race conditions). https://review.coreboot.org/c/coreboot/+/63566/comment/cf6e5515_cf15197c PS5, Line 985: goto finish; Reverse the if condition and avoid goto. -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 11:35:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michael Niewöhner (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 8: (12 comments) File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/ade03ec3_3559025f PS3, Line 3: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, > Line removed Done https://review.coreboot.org/c/coreboot/+/62498/comment/ad56c84e_e235a1e0 PS3, Line 33: # Acoustic settings > Comment removed Done File src/mainboard/clevo/tgl-u/variants/nv40mz/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62498/comment/fb3e508c_91552bda PS6, Line 3: bootblock-y += gpio.c : : romstage-y += romstage.c : : ramstage-y += gpio.c : ramstage-y += hda_verb.c : > File removed Done File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/0365bb60_8e5770b8 PS6, Line 17: register "external_bypass" = "1" > Looks like both are unpopulated I expected that :D same on other devices... -> external bypass settings and FIVR settings in the dt can be completely dropped then https://review.coreboot.org/c/coreboot/+/62498/comment/687128b7_fd48f262 PS6, Line 261: Pantone ROM > Some models ship with a Pantone-validated display. […] I guess it's not only validated but calibrated and this eeprom probably contains the calibration data File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/81a51f69_f699abc4 PS6, Line 210: PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), > Changed to `PAD_NC` Done File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c: https://review.coreboot.org/c/coreboot/+/62498/comment/0c8ae2e2_296906c6 PS6, Line 9: * Disable AER for the SSD slot to support S0ix with SSDs running : * buggy firmware : > Samsung 980 (non-pro) SSD causes the laptop to fail to wake from s0ix standby while AER is enabled. […] ouch... Thanks, I'll have to check that on l140mu... https://review.coreboot.org/c/coreboot/+/62498/comment/fafc0492_a59c792d PS6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0; > Added both params Done File src/mainboard/clevo/tgl-u/variants/nv4x/gpio_early.c: https://review.coreboot.org/c/coreboot/+/62498/comment/c4dd87fc_24ed29e6 PS3, Line 11: PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), /* DGPU_RST#_PCH */ : PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), /* DGPU_PWR_EN */ > Switched to `PAD_CFG_GPO` Done File src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/4e818264_32899dc3 PS3, Line 4: # TODO: Check if this is correct > Right, removed the entire power limit config Done https://review.coreboot.org/c/coreboot/+/62498/comment/6941e008_c6df18e1 PS3, Line 3: # Power limits : # TODO: Check if this is correct : register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ : .tdp_pl1_override = 10, : .tdp_pl2_override = 20, : }" : register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ : .tdp_pl1_override = 10, : .tdp_pl2_override = 20, : }" > Dropped Done https://review.coreboot.org/c/coreboot/+/62498/comment/adce1877_e8aaaa2a PS3, Line 42: register "HybridStorageMode" = "0" > Removed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 11:27:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
by Michał Żygowski (Code Review) 05 May '22

05 May '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64074 ) Change subject: soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading ...................................................................... soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on Slimbootloader: Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib TEST=Not yet working, HECI returns an error in the MKHI header. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c A src/soc/intel/alderlake/hsphy.c A src/soc/intel/alderlake/include/soc/hsphy.h 4 files changed, 248 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/64074/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index fce0681..1b945eb 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += hsphy.c ramstage-y += lockdown.c ramstage-y += me.c ramstage-y += p2sb.c diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index bb7142c..f84d2cb 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -12,6 +12,7 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> +#include <soc/hsphy.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -166,6 +167,9 @@ void soc_init_pre_device(void *chip_info) { + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + load_and_init_hsphy(); + /* Perform silicon specific init. */ fsp_silicon_init(); diff --git a/src/soc/intel/alderlake/hsphy.c b/src/soc/intel/alderlake/hsphy.c new file mode 100644 index 0000000..cf2f1c0 --- /dev/null +++ b/src/soc/intel/alderlake/hsphy.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <assert.h> +#include <stdlib.h> +#include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/cse.h> +#include <soc/hsphy.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <vb2_api.h> +#include <lib.h> + +#define HASHALG_SHA1 0x00000001 +#define HASHALG_SHA256 0x00000002 +#define HASHALG_SHA384 0x00000003 +#define HASHALG_SHA512 0x00000004 + +#define MAX_HASH_SIZE 64 // 64 is max size for SHA512 + +#define GET_IP_FIRMWARE_CMD 0x21 + +#define HSPHY_PAYLOAD_SIZE 32*KiB + +#define CPU_PID_PCIE_PHYX16_BROADCAST 0x55 + +struct ip_push_model { + uint16_t count; + union { + uint16_t address; + uint16_t type; // Valid only for Extended mode push model operations + } mode; + uint32_t data[0]; +}; + +static void *pcr_reg_address(uint8_t pid, uint16_t offset) +{ + uintptr_t reg_addr; + + /* Create an address based off of port id and offset. */ + reg_addr = REG_BASE_ADDRESS; + reg_addr += ((uintptr_t)pid) << 16; + reg_addr += (uintptr_t)offset; + + return (void *)reg_addr; +} + +static void cpu_pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata) +{ + /* Ensure the PCR offset is correctly aligned. */ + assert(IS_ALIGNED(offset, sizeof(indata))); + + write32(pcr_reg_address(pid, offset), indata); +} + +static int heci_get_hsphy_payload(void *buf, uint32_t *buf_size, uint8_t *hash_buf, + uint8_t *hash_alg) +{ + size_t reply_size; + + struct heci_ip_load_request { + struct mkhi_hdr hdr; + uint32_t version; + uint32_t operation; + uint32_t dram_base_low; + uint32_t dram_base_high; + uint32_t memory_size; + uint32_t reserved; + } __packed msg = { + .hdr = { + .group_id = MKHI_GROUP_ID_BUP_COMMON, + .command = GET_IP_FIRMWARE_CMD, + }, + .version = 1, + .operation = 1, + .dram_base_low = (uintptr_t)buf, + .dram_base_high = 0, + .memory_size = *buf_size, + .reserved = 0, + }; + + struct heci_ip_load_response { + struct mkhi_hdr hdr; + uint32_t payload_size; + uint32_t reserved[2]; + uint32_t status; + uint8_t hash_type; + uint8_t hash[MAX_HASH_SIZE]; + } __packed reply; + + if (!buf || !buf_size || !hash_buf || !hash_alg) { + printk(BIOS_ERR, "%s: Invalid parameters\n", __func__); + return -1; + } + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + if (heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, HECI_MKHI_ADDR)) { + printk(BIOS_ERR, "HECI: Get IP firmware failed\n"); + return -1; + } + + hexdump(&reply, sizeof(reply)); + + if (reply.hdr.result) { + printk(BIOS_ERR, "HECI: Get IP firmware response invalid\n"); + return -1; + } + + *buf_size = reply.payload_size; + *hash_alg = reply.hash_type; + memcpy(hash_buf, reply.hash, MAX_HASH_SIZE); + + printk(BIOS_DEBUG, "HECI: Get IP firmware success. Response:\n"); + printk(BIOS_DEBUG, " Payload size = 0x%x\n", *buf_size); + printk(BIOS_DEBUG, " Hash type used for signing payload = 0x%x\n", *hash_alg); + + return 0; +} + +static int verify_hsphy_hash(void *buf, uint32_t buf_size, uint8_t *hash_buf, uint8_t hash_alg) +{ + enum vb2_hash_algorithm alg; + uint32_t hash_size; + uint8_t hash_calc[MAX_HASH_SIZE]; + + switch (hash_alg) { + case HASHALG_SHA256: + alg = VB2_HASH_SHA256; + hash_size = VB2_SHA256_DIGEST_SIZE; + break; + case HASHALG_SHA384: + alg = VB2_HASH_SHA384; + hash_size = VB2_SHA384_DIGEST_SIZE; + break; + case HASHALG_SHA512: + alg = VB2_HASH_SHA512; + hash_size = VB2_SHA512_DIGEST_SIZE; + break; + case HASHALG_SHA1: + default: + printk (BIOS_ERR, "Hash alg %d not supported, try SHA384\n", hash_alg); + alg = VB2_HASH_SHA384; + hash_size = VB2_SHA384_DIGEST_SIZE; + break; + } + + if (vb2_digest_buffer(buf, buf_size, alg, hash_calc, hash_size)) { + printk(BIOS_ERR, "HSPHY SHA calculation failed\n"); + return -1; + } + + if (memcmp(hash_buf, hash_calc, hash_size)) { + printk(BIOS_ERR, "HSPHY SHA hashes do not match\n"); + hexdump(hash_buf, hash_size); + hexdump(hash_calc, hash_size); + return -1; + } + + return 0; +} + +static void upload_hsphy_to_cpu_pcie(void *buf, uint32_t buf_size) +{ + uint32_t i = 0, j = 0; + struct ip_push_model *push_model = (struct ip_push_model *)buf; + + while (i < buf_size) { + i += sizeof (*push_model); + + if ((push_model->mode.type == 0) && (push_model->count == 0)) { + break; // End of file + } + + for (j = 0; j < push_model->count; j++) { + cpu_pcr_write32(CPU_PID_PCIE_PHYX16_BROADCAST, + push_model->mode.address, + push_model->data[j]); + i += sizeof (uint32_t); + } + + push_model = (struct ip_push_model *)(buf + i); + } +} + +void load_and_init_hsphy(void) +{ + void *hsphy_buf; + uint8_t hsphy_hash[MAX_HASH_SIZE]; + uint8_t hash_type; + uint32_t buf_size = HSPHY_PAYLOAD_SIZE; + pci_devfn_t dev = PCH_DEV_CSE; + uint16_t pci_cmd_bme_mem = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + + hsphy_buf = malloc(HSPHY_PAYLOAD_SIZE); + + if (!hsphy_buf) { + printk(BIOS_ERR, "Could not allocate memory for HSPHY blob\n"); + return; + } + + memset(hsphy_buf, 0, HSPHY_PAYLOAD_SIZE); + + if (!is_cse_enabled()) { + printk(BIOS_ERR, "%s: CSME not enabled or not visible\n", __func__); + return; + } + + /* Ensure BAR, BME and memory space are enabled */ + if ((pci_read_config16(dev, PCI_COMMAND) & pci_cmd_bme_mem) != pci_cmd_bme_mem) + pci_or_config16(dev, PCI_COMMAND, pci_cmd_bme_mem); + + + if (pci_read_config32(dev, PCI_BASE_ADDRESS_0) == 0) { + pci_and_config16(dev, PCI_COMMAND, ~pci_cmd_bme_mem); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); + pci_or_config16(dev, PCI_COMMAND, pci_cmd_bme_mem); + } + + if (heci_get_hsphy_payload(hsphy_buf, &buf_size, hsphy_hash, &hash_type)) + return; + + if (verify_hsphy_hash(hsphy_buf, buf_size, hsphy_hash, hash_type)) + return; + + upload_hsphy_to_cpu_pcie(hsphy_buf, buf_size); + + free(hsphy_buf); +} diff --git a/src/soc/intel/alderlake/include/soc/hsphy.h b/src/soc/intel/alderlake/include/soc/hsphy.h new file mode 100644 index 0000000..9974afe --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/hsphy.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_HSPHY_H_ +#define _SOC_ALDERLAKE_HSPHY_H_ + +void load_and_init_hsphy(void); + +#endif /* _SOC_ALDERLAKE_HSPHY_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Gerrit-Change-Number: 64074 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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