coreboot-gerrit May 2022

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Change in coreboot[master]: cpu/intel/model_2065x: Drop unused function declaration
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64046 ) Change subject: cpu/intel/model_2065x: Drop unused function declaration ...................................................................... cpu/intel/model_2065x: Drop unused function declaration Looks like the `set_power_limits()` declaration is copy-pasta leftovers from `cpu/intel/model_206ax`. As it's unused, get rid of it. Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/model_2065x.h 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 251fd75..92cc55c 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -53,9 +53,6 @@ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) # error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" -- To view, visit https://review.coreboot.org/c/coreboot/+/64046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b Gerrit-Change-Number: 64046 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: Remove unused i2c7 settings
by Felix Held (Code Review) 05 May '22

05 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63892 ) Change subject: mb/google/brya/var/vell: Remove unused i2c7 settings ...................................................................... mb/google/brya/var/vell: Remove unused i2c7 settings This patch removes unused i2c7 settings. Accroding to EVT schematic, i2c7 is reserved for AMP but resistors are unstuffing. BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 5 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Robert Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index 57f8564..a984a5a 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -57,10 +57,10 @@ PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), - /* H12 : I2C7_SDA ==> UWB_SDA */ - PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG), - /* H13 : I2C7_SCL ==> UWB_SCL */ - PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG), + /* H12 : Reserved I2C7_SDAL for AMP */ + PAD_NC(GPP_H12, NONE), + /* H13 : Reserved I2C7_SCL for AMP */ + PAD_NC(GPP_H13, NONE), /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index aa8350f..c7f985c 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -57,15 +57,6 @@ .fall_time_ns = 400, .data_hold_time_ns = 50, }, - .i2c[7] = { - .speed = I2C_SPEED_FAST_PLUS, - .speed_config[0] = { - .speed = I2C_SPEED_FAST_PLUS, - .scl_lcnt = 45, - .scl_hcnt = 30, - .sda_hold = 20, - }, - }, }" register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" @@ -83,7 +74,7 @@ [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexI2C7] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoDisabled, }" device domain 0 on device ref igpu on @@ -358,7 +349,6 @@ device i2c 15 on end end end - device ref i2c7 on end device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" -- To view, visit https://review.coreboot.org/c/coreboot/+/63892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff Gerrit-Change-Number: 63892 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Angel Pons (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 14: (1 comment) File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/17c037fc_96bb6a1c PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ : > Oh, sorry, I should have been more clear. It should be configured in both. FSP would override the early settings when the GPIO isn't configured in ramstage. Huh, FSP shouldn't reconfigure the GPIOs... -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 05 May 2022 17:31:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Enable HPD and DDC for DP
by Angel Pons (Code Review) 05 May '22

05 May '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64079 ) Change subject: mb/prodrive/atlas: Enable HPD and DDC for DP ...................................................................... Patch Set 1: (1 comment) File src/mainboard/prodrive/atlas/devicetree.cb: https://review.coreboot.org/c/coreboot/+/64079/comment/8ba203f9_bc11d78f PS1, Line 88: [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, To do: Also configure this for TCP0 and TCP1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a380eb02b73049386e833ca7acc3c44f4f2cfee Gerrit-Change-Number: 64079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 17:22:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Use wait_finished_mp_run_on_all_cpus for APs MTRR init
by Tim Wawrzynczak (Code Review) 05 May '22

05 May '22

Attention is currently required from: Subrata Banik, Kane Chen, Arthur Heymans. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63567 ) Change subject: soc/intel/common: Use wait_finished_mp_run_on_all_cpus for APs MTRR init ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: Thanks Kane! -- To view, visit https://review.coreboot.org/c/coreboot/+/63567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26 Gerrit-Change-Number: 63567 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Thu, 05 May 2022 17:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Tim Wawrzynczak (Code Review) 05 May '22

05 May '22

Attention is currently required from: Arthur Heymans, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63566 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63566/comment/d68d8c4f_7d8e1cb5 PS7, Line 866: same -- To view, visit https://review.coreboot.org/c/coreboot/+/63566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Gerrit-Change-Number: 63566 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 May 2022 17:21:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Enable HPD and DDC for DP
by Angel Pons (Code Review) 05 May '22

05 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64079 ) Change subject: mb/prodrive/atlas: Enable HPD and DDC for DP ...................................................................... mb/prodrive/atlas: Enable HPD and DDC for DP Enable HPD and DDC for DisplayPort outputs. Change-Id: I9a380eb02b73049386e833ca7acc3c44f4f2cfee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/64079/1 diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 6dfb8a2..8c775fe 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -83,6 +83,11 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, }" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end -- To view, visit https://review.coreboot.org/c/coreboot/+/64079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a380eb02b73049386e833ca7acc3c44f4f2cfee Gerrit-Change-Number: 64079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/crota: Fix codec reset pin in overridetree
by Terry Chen (Code Review) 05 May '22

05 May '22

Attention is currently required from: Paul Menzel. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64043 ) Change subject: mb/google/brya/var/crota: Fix codec reset pin in overridetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64043/comment/3f20d590_96547ba9 PS2, Line 9: Crota360 is using a Cirrus CS42L42 for its audio codec; it : requires the reset pin to be deasserted in ramstage for proper : power sequencing. > Please reflow for 72 characters per line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Gerrit-Change-Number: 64043 Gerrit-PatchSet: 3 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 05 May 2022 16:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/crota: Fix codec reset pin in overridetree
by Terry Chen (Code Review) 05 May '22

05 May '22

Attention is currently required from: Terry Chen. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64043 to look at the new patch set (#3). Change subject: mb/google/brya/var/crota: Fix codec reset pin in overridetree ...................................................................... mb/google/brya/var/crota: Fix codec reset pin in overridetree Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/64043/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Gerrit-Change-Number: 64043 Gerrit-PatchSet: 3 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michael Niewöhner (Code Review) 05 May '22

05 May '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 14: (2 comments) File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62498/comment/83360bc6_e966eee9 PS1, Line 58: register "LpmStateDisableMask" = " : LPM_S0i2_1 | : LPM_S0i2_2 | : LPM_S0i3_1 | : LPM_S0i3_2 | : LPM_S0i3_3 | : LPM_S0i3_4 : > Vendor firmware does this, I assumed there was a reason for it, but maybe there isn't? :D -> see Michal's and my discussion in matrix ;) Intel docs don't state any specific requirements, so *probably* no need to disable s0i2.1. Who knows, maybe vendor fw has some problem caused by whatever... :S File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/8444c69a_7e9947d4 PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ : > Right, removed them from `gpio.c` altogether. Oh, sorry, I should have been more clear. It should be configured in both. FSP would override the early settings when the GPIO isn't configured in ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 05 May 2022 16:22:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2022