coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
by Rex-BC Chen (Code Review) 04 May '22

04 May '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64038 ) Change subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64038/comment/8aeccffe_fb9853fb PS1, Line 9: We encountered a delay issue when powering down. The root cause is : the incorrect setting for delay time. : : The meaning of PMIC_CPSDSA4[4:0] is: power down at specified time slot. : If PMIC_CPSDSA4[4:0] is 0xA, in this time slot, it cause delay 20ms : comparing with 0xF. : : To resolve this issue, we need to change to correct time slot. : Therefore, we change the value from 0xA to 0xF. > PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Gerrit-Change-Number: 64038 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 03:51:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
by Rex-BC Chen (Code Review) 04 May '22

04 May '22

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Change in coreboot[master]: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
by Rex-BC Chen (Code Review) 04 May '22

04 May '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64038 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF ...................................................................... soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF. To avoid the delay, change the value from 0xA to 0xF. This modification is based on chapter 3.7 in the MT8186 functional specification. BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct. Signed-off-by: zhiyong tao <zhiyong.tao(a)mediatek.corp-partner.google.com> Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/64038/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Gerrit-Change-Number: 64038 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd: Demote log about using default DDR4 params to NOTICE
by Eric Lai (Code Review) 04 May '22

04 May '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Ivy Jian, Julius Werner. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63774 ) Change subject: lib/spd: Demote log about using default DDR4 params to NOTICE ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Yes, so I think error is not necessary, warning or notice should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/63774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6 Gerrit-Change-Number: 63774 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 05 May 2022 03:29:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: allow MKBP devices and disable TBMC device
by Ian Feng (Code Review) 04 May '22

04 May '22

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64066 ) Change subject: mb/google/skyrim: allow MKBP devices and disable TBMC device ...................................................................... mb/google/skyrim: allow MKBP devices and disable TBMC device Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:230682161 TEST=manual test on Skyrim: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001 --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/64066/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h index f10146d..ea6b93e 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -58,8 +58,8 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GEVENT_5 /* AGPIO 11 -> GPE 5 */ -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001 Gerrit-Change-Number: 64066 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd: Demote log about using default DDR4 params to NOTICE
by Reka Norman (Code Review) 04 May '22

04 May '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Ivy Jian, Julius Werner, Eric Lai. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63774 ) Change subject: lib/spd: Demote log about using default DDR4 params to NOTICE ...................................................................... Patch Set 5: (1 comment) Patchset: PS1: > The stress test just check there no error in FW log. […] I agree that the process for getting SPD info isn't great. E.g. for LPDDR5, there is no new SPD spec, so we're still using the LPDDR3/4 spec plus whatever modifications SoC vendors make to support LPDDR5. But whether or not getting the info is easy, we still need to do it as part of the bringup so that we can update spd_tools and smbios. So once we have the info, we might as well update this too, right? And it seems helpful to have a test to remind us to do that. -- To view, visit https://review.coreboot.org/c/coreboot/+/63774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6 Gerrit-Change-Number: 63774 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 May 2022 03:25:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: fix tcss_usb3 port
by Casper Chang (Code Review) 04 May '22

04 May '22

Attention is currently required from: Casper Chang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64039 to look at the new patch set (#2). Change subject: mb/google/brask/variants/moli: fix tcss_usb3 port ...................................................................... mb/google/brask/variants/moli: fix tcss_usb3 port fix tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/64039/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Gerrit-Change-Number: 64039 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Ravishankar Sarawadi (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Paul Menzel, Angel Pons, Raj Astekar, Ravishankar Sarawadi. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... Patch Set 14: (3 comments) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62772/comment/72a338ea_22ca15e0 PS13, Line 51: Platform FSP integration guide document > Not yet, so keeping it same as ADL for now. Done File src/soc/intel/meteorlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/62772/comment/837060f2_6fb5db40 PS13, Line 63: : #define IOE_PCR_ABOVE_4G_BASE_ADDR 0x3fff0000000 : #define IOE_P2SB_BAR IOE_PCR_ABOVE_4G_BASE_ADDR : #define IOE_P2SB_SIZE (256 * MiB) : : #define IOM_BASE_ADDR 0x3fff0aa0000 : #define IOM_BASE_SIZE 0x1600 : #define IOM_BASE_ADDR_MAX 0x3fff0aa15ff > Yes, for TCSS functionality based on IOE. Done File src/soc/intel/meteorlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/62772/comment/daaa52ca_77358ca6 PS13, Line 186: //#define PCH_DEV_SLOT_LPC PCI_DEV_SLOT_ESPI > Right, it's not needed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ethan Tsao <ethan.tsao(a)intel.corp-partner.google.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 May 2022 02:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Ravishankar Sarawadi (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Paul Menzel, Angel Pons, Raj Astekar, Ravishankar Sarawadi. Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Angel Pons, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62772 to look at the new patch set (#15). Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock Base code is based of Intel Alder Lake SOC code. List of changes: 1. Add required Meteor Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include MTL-P related DID, BDF 4. Ref: Processor EDS documents vol1 #621483, vol2 #640858 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 --- M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/meteorlake/Kconfig A src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/bootblock/bootblock.c A src/soc/intel/meteorlake/bootblock/ioe_die.c A src/soc/intel/meteorlake/bootblock/report_platform.c A src/soc/intel/meteorlake/bootblock/soc_die.c A src/soc/intel/meteorlake/include/soc/bootblock.h A src/soc/intel/meteorlake/include/soc/espi.h A src/soc/intel/meteorlake/include/soc/iomap.h A src/soc/intel/meteorlake/include/soc/p2sb.h A src/soc/intel/meteorlake/include/soc/pci_devs.h A src/soc/intel/meteorlake/include/soc/pcr_ids.h A src/soc/intel/meteorlake/include/soc/pm.h A src/soc/intel/meteorlake/include/soc/smbus.h 15 files changed, 1,034 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 15 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ethan Tsao <ethan.tsao(a)intel.corp-partner.google.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Ravishankar Sarawadi (Code Review) 04 May '22

04 May '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Paul Menzel, Angel Pons, Raj Astekar, Ravishankar Sarawadi. Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Angel Pons, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62772 to look at the new patch set (#14). Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock Base code is based of Intel Alder Lake SOC code. List of changes: 1. Add required Meteor Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include MTL-P related DID, BDF 4. Ref: Processor EDS documents vol1 #621483, vol2 #640858 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 --- M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/meteorlake/Kconfig A src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/bootblock/bootblock.c A src/soc/intel/meteorlake/bootblock/ioe_die.c A src/soc/intel/meteorlake/bootblock/report_platform.c A src/soc/intel/meteorlake/bootblock/soc_die.c A src/soc/intel/meteorlake/include/soc/bootblock.h A src/soc/intel/meteorlake/include/soc/espi.h A src/soc/intel/meteorlake/include/soc/iomap.h A src/soc/intel/meteorlake/include/soc/p2sb.h A src/soc/intel/meteorlake/include/soc/pci_devs.h A src/soc/intel/meteorlake/include/soc/pcr_ids.h A src/soc/intel/meteorlake/include/soc/pm.h A src/soc/intel/meteorlake/include/soc/smbus.h 15 files changed, 1,033 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ethan Tsao <ethan.tsao(a)intel.corp-partner.google.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2022