coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
by Elyes Haouas (Code Review) 07 Mar '22

07 Mar '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62647 ) Change subject: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values ...................................................................... include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb --- M src/include/spd.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62647/1 diff --git a/src/include/spd.h b/src/include/spd.h index 8493d40..ca78d9c 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -236,8 +236,8 @@ DDR4_SPD_LRDIMM = 0x04, DDR4_SPD_MINI_RDIMM = 0x05, DDR4_SPD_MINI_UDIMM = 0x06, - DDR4_SPD_72B_SO_UDIMM = 0x08, - DDR4_SPD_72B_SO_RDIMM = 0x09, + DDR4_SPD_72B_SO_RDIMM = 0x08, + DDR4_SPD_72B_SO_UDIMM = 0x09, DDR4_SPD_16B_SO_DIMM = 0x0c, DDR4_SPD_32B_SO_RDIMM = 0x0d, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Gerrit-Change-Number: 62647 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
by Elyes Haouas (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jakub Czapiga, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Jakub Czapiga, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62181 to look at the new patch set (#5). Change subject: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} ...................................................................... src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/ddr2.h M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/spd.h M src/mainboard/scaleway/tagada/ramstage.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M tests/lib/dimm_info_util-test.c 12 files changed, 97 insertions(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62181/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Gerrit-Change-Number: 62181 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
by Elyes Haouas (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jakub Czapiga, Angel Pons, Patrick Rudolph. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62181 ) Change subject: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62181/comment/6d657c89_74bf4d96 PS4, Line 9: While on it, fix SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM and SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM values : respectively to 0x08 and 0x09. > Please do this in a separate commit. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Gerrit-Change-Number: 62181 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: drop orphaned VR domains enum
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Paul Menzel, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62622 ) Change subject: soc/intel/tgl: drop orphaned VR domains enum ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: the arrays were dropped in commit bae2d554373baca1023 (which is correct, TGL only has 1 VR domain, VCCIN) -- To view, visit https://review.coreboot.org/c/coreboot/+/62622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Gerrit-Change-Number: 62622 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Hung-Te Lin (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/f5c8ad23_28cf9375 PS9, Line 14: 100ms > a hacky implementation: we can assume the pre-init should be done very early in the bootblock, for e […] Looking at a typical 8195 boot timeline: - entire bootblock takes 68ms - verstage takes 250ms - romstage takes 210ms So the ramstage is really unlikely to start less than 100ms. Another trick is maybe we can also save the time execution time of romstage, to the ddrinfo, so it'd be pretty easy to make sure there's enough latency. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Hello Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#5). Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variables to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 41 files changed, 284 insertions(+), 279 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/starlabs: Add LabTop Mk III
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58538 ) Change subject: mainboard/starlabs: Add LabTop Mk III ...................................................................... Patch Set 55: (5 comments) This change is ready for review. File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/58538/comment/f0584085_22f367b1 PS50, Line 20: BOARD_STARLABS_LABTOP_KBL > SOC_INTEL_COMMON_SKYLAKE_BASE Done File src/mainboard/starlabs/labtop/variants/kbl/board.fmd: https://review.coreboot.org/c/coreboot/+/58538/comment/2f1ddd6d_e49836c0 PS50, Line 2: # Manually defined FMD in order to ensure that space is reserved for the EC > I don't see any regions for the EC firmware. […] Removed the comment but would prefer to keep it - seen strange behaviour when changing layouts. File src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/58538/comment/8314fd14_e0c30538 PS50, Line 53: register "PcieRpClkReqNumber[0]" = "0xFF" : register "PcieRpClkReqNumber[1]" = "0xFF" : register "PcieRpClkReqNumber[2]" = "0xFF" : register "PcieRpClkReqNumber[3]" = "0xFF" : register "PcieRpClkReqNumber[4]" = "0xFF" : register "PcieRpClkReqNumber[6]" = "0xFF" > Shouldn't be needed if `PcieRpClkReqSupport` is not set. Done https://review.coreboot.org/c/coreboot/+/58538/comment/c13fb702_78a4c382 PS50, Line 77: # Internal Webcam : register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" : # Daughterboard SD Card : register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" : # Internal Bluetooth : register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" > Internal USB ports shouldn't be assigned to an overcurrent pin Done https://review.coreboot.org/c/coreboot/+/58538/comment/3b975b8b_bd38fe60 PS50, Line 189: subsystemid 0x10ec 0x111e > This sets the subsystem ID for the HDA PCI device, not the codec. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Gerrit-Change-Number: 58538 Gerrit-PatchSet: 55 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:19:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Hung-Te Lin (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/905d50e7_dd4fca7a PS9, Line 14: 100ms > Agree with Angel's concern. […] a hacky implementation: we can assume the pre-init should be done very early in the bootblock, for example within 10ms or even 100ms, and then call get_us_since_boot() before next pcie init, to make sure there's enough delay. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add prompt for Boot Timeout
by Matt DeVillier (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Martin Roth, Stefan Reinauer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62558 ) Change subject: payloads/tianocore: Add prompt for Boot Timeout ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b8f0a9b5bc0796506b991199a457d6b34ae494 Gerrit-Change-Number: 62558 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:14:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Kangheui Won, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62570 ) Change subject: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Gerrit-Change-Number: 62570 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:14:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022