coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Hello Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#4). Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variables to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 41 files changed, 283 insertions(+), 278 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Add FW_CONFIG Definition
by Raul Rangel (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Bhanu Prakash Maiya, Jon Murphy, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62626 ) Change subject: mb/google/skyrim: Add FW_CONFIG Definition ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 Gerrit-Change-Number: 62626 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:57:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 99: Code-Review+2 (1 comment) File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/58428/comment/bfa35759_dc4d64d7 PS98, Line 20: BOARD_STARLABS_LABTOP_CML > `SOC_INTEL_CANNONLAKE_BASE` so that you don't need to touch this when new boards get added Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 99 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:54:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Rename infrastructure section
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62441 ) Change subject: Documentation: Rename infrastructure section ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba8a2e2070a79d8c9e955133203f9bb9f58cb8e Gerrit-Change-Number: 62441 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:54:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 98: (1 comment) File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/58428/comment/f89afa67_937e8eed PS98, Line 24: BOARD_STARLABS_STARBOOK_TGL > `SOC_INTEL_TIGERLAKE`, same reason as above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 98 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 98: Code-Review+1 (3 comments) File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/58428/comment/fd89484f_afcdc82d PS95, Line 19: EC_STARLABS_FAN > Remove as all boards in the series will use a fan. CB:62124 File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/58428/comment/d550a67f_a4921bc8 PS98, Line 20: BOARD_STARLABS_LABTOP_CML `SOC_INTEL_CANNONLAKE_BASE` so that you don't need to touch this when new boards get added https://review.coreboot.org/c/coreboot/+/58428/comment/f97bbd09_8c708ce2 PS98, Line 24: BOARD_STARLABS_STARBOOK_TGL `SOC_INTEL_TIGERLAKE`, same reason as above -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 98 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:51:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent
by Raul Rangel (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jason Glenesk, Damien Zammit, Jakub Czapiga, Lee Leahy, Marshall Dawson, Angel Pons, Julius Werner, Andrey Petrov, Fred Reitberger, Patrick Rudolph, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62019 ) Change subject: timestamps: Rename timestamps to make names more consistent ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Gerrit-Change-Number: 62019 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:48:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apollolake: Hook up CnviMode to devicetree
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62127 ) Change subject: soc/apollolake: Hook up CnviMode to devicetree ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62127/comment/b70b1a93_7946826b PS3, Line 7: DeviceTree > nit: coreboot's devicetree is spelled in lowercase Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Gerrit-Change-Number: 62127 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apollolake: Hook up CnviMode to devicetree
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Andy Pont, Angel Pons, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62127 to look at the new patch set (#4). Change subject: soc/apollolake: Hook up CnviMode to devicetree ...................................................................... soc/apollolake: Hook up CnviMode to devicetree Hook PCH_DEVFN_CNVI (0c.0) to CnviMode. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 --- M src/soc/intel/apollolake/chip.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62127/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Gerrit-Change-Number: 62127 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and ...
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61887 ) Change subject: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix ...................................................................... mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix This change is to move MPTS (Mainboard Prepare To Sleep) method from wwan_power.asl to SSDT. MPTS is mainboard-specific method, while wwan_power.asl is meant for WWAN from its name. Having fixed MPTS method (i.e. DSDT) can not cover the case where device only presents and certain CBI bit(s) is(are) set. In Redrix and Brya, there are SKUs with or without 5G, 4G device. For those with 4G, MPTS method should be different. For those with no WWAN device, no MPTS is needed. Having MPTS generating in SSDT also eliminates the need for introducing Kconfig flags to support different devices in the future. MPTS method is created inside mainboard_fill_ssdt function in which the corresponding variant function is called. This will generate the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP01.PXSX.DPTS (Arg0) } } } Test: Check the SSDT for MPTS method under \_SB after boot to OS Use shutdown command and check the GPIO pins from logical analyzer Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/mainboard.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 7 files changed, 55 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7235b03..f88f429 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -36,8 +36,6 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA - select HAVE_PCIE_WWAN - select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG @@ -46,8 +44,6 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA - select HAVE_PCIE_WWAN - select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG @@ -118,8 +114,6 @@ select DRIVERS_I2C_MAX98390 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select HAVE_PCIE_WWAN - select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_REDRIX4ES @@ -132,8 +126,6 @@ select DRIVERS_I2C_MAX98390 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select HAVE_PCIE_WWAN - select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_TAEKO diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 536eabc..488eb88 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -5,6 +5,10 @@ #include <ec/ec.h> #include <soc/ramstage.h> #include <fw_config.h> +#include <acpi/acpigen.h> +#include <drivers/wwan/fm/chip.h> + +WEAK_DEV_PTR(rp6_wwan); static void add_fw_config_oem_string(const struct fw_config *config, void *arg) { @@ -55,10 +59,54 @@ mainboard_ec_init(); } +static void mainboard_generate_shutdown(const struct device *dev) +{ + const struct drivers_wwan_fm_config *config = config_of(dev); + const struct device *parent = dev->bus->dev; + + if (!config) + return; + if (config->rtd3dev) { + acpigen_write_store(); + acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + { + acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS")); + acpigen_emit_byte(ARG0_OP); + } + acpigen_write_if_end(); + } else { + acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS")); + acpigen_emit_byte(ARG0_OP); + } +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + const struct device *wwan = DEV_PTR(rp6_wwan); + + if (wwan) { + acpigen_write_scope("\\_SB"); + acpigen_write_method_serialized("MPTS", 1); + mainboard_generate_shutdown(wwan); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ + } + /* for variant to fill additional SSDT */ + variant_fill_ssdt(dev); +} + +void __weak variant_fill_ssdt(const struct device *dev) +{ + /* Add board-specific SSDT entries */ +} + static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; dev->ops->get_smbios_strings = mainboard_smbios_strings; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index b3a10e0..7c1ce21 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -23,6 +23,7 @@ int variant_memory_sku(void); bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config); +void variant_fill_ssdt(const struct device *dev); /* Modify devictree settings during ramstage */ void variant_devtree_update(void); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 9f3e028..d18e9df 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -198,7 +198,7 @@ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" use rp6_rtd3 as rtd3dev - device generic 0 on + device generic 0 alias rp6_wwan on probe DB_LTE LTE_PCIE end end diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 13d028e..ac968ba 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -195,7 +195,7 @@ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" use rp6_rtd3 as rtd3dev - device generic 0 on + device generic 0 alias rp6_wwan on probe DB_LTE LTE_PCIE end end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 62a24ed..2bf3fc2 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -92,6 +92,7 @@ }, }" register "tcc_offset" = "3" # TCC of 97C + device domain 0 on device ref igpu on chip drivers/gfx/generic @@ -178,7 +179,7 @@ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" use rp6_rtd3 as rtd3dev - device generic 0 on + device generic 0 alias rp6_wwan on probe DB_LTE LTE_PCIE end end diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 5cb105d..afffab5 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -78,6 +78,7 @@ }, }" register "tcc_offset" = "3" # TCC of 97C + device domain 0 on device ref igpu on chip drivers/gfx/generic @@ -164,7 +165,7 @@ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" use rp6_rtd3 as rtd3dev - device generic 0 on + device generic 0 alias rp6_wwan on probe DB_LTE LTE_PCIE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/61887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Gerrit-Change-Number: 61887 Gerrit-PatchSet: 16 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022