Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62263 )
Change subject: soc/intel/alderlake: Define Kconfigs for Descriptor Region
......................................................................
soc/intel/alderlake: Define Kconfigs for Descriptor Region
The patch defines Kconfigs for FMAP Descriptor Region and Descriptor
Region size. The Kconfigs will be used by follow-up patches.
TEST=Build Brya code
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 12 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Maulik V Vaghela: Looks good to me, but someone else must approve
Krishna P Bhat D: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4ced781..0484b17 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -368,4 +368,16 @@
endif
+config SI_DESC_REGION
+ string "Descriptor Region name"
+ default "SI_DESC"
+ help
+ Name of Descriptor Region in the FMAP
+
+config SI_DESC_REGION_SZ
+ int
+ default 4096
+ help
+ Size of Descriptor Region in the FMAP
+
endif
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62629 )
Change subject: soc/intel/alderlake: Allow mainboard to configure C1 state auto-demotion
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/62629/comment/13f62cc5_59dae7e3
PS4, Line 572: DisableC1StateAutoDemotion
> > Yes Subrata...I just wanted to align with syntax in entire file. […]
Do you want to put CB:62645 at the top of this patch train? (thanks BTW!!!)
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62574 )
Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 7: Code-Review+2
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Change subject: [WIP]mb/prodrive/hermes: Change gfx init depending on eeprom config
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/hermes/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143383):
https://review.coreboot.org/c/coreboot/+/62649/comment/d973ea43_82d4f3fa
PS1, Line 290: dev = dev_find_device(PCI_VENDOR_ID_ASPEED, PCI_DEVICE_ID_ASPEED_AST2050_VGA, NULL);
line over 96 characters
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62649
to review the following change.
Change subject: [WIP]mb/prodrive/hermes: Change gfx init depending on eeprom config
......................................................................
[WIP]mb/prodrive/hermes: Change gfx init depending on eeprom config
untested
Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/prodrive/hermes/mainboard.c
1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62649/1
diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c
index 2f0de61..d363c77 100644
--- a/src/mainboard/prodrive/hermes/mainboard.c
+++ b/src/mainboard/prodrive/hermes/mainboard.c
@@ -8,6 +8,7 @@
#include <crc_byte.h>
#include <device/device.h>
#include <device/dram/spd.h>
+#include <device/pci_ids.h>
#include <drivers/intel/gma/opregion.h>
#include <gpio.h>
#include <intelblocks/gpio.h>
@@ -257,3 +258,38 @@
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL);
+
+enum internale_gfx {
+ PRIMARY_VIDEO_ASPEED = 0,
+ PRIMARY_VIDEO_INTEL = 1,
+};
+
+static void disable_internal_gfx(struct device *dev)
+{
+ if (!dev)
+ return;
+ dev->ops->init = NULL;
+}
+
+/*
+ * In the current setup with EDK2 as a payload, only the Intel GFX or Aspeed one is set up by
+ * coreboot. The other ones are set up as GOP by the payload. The coreboot tables handoff only
+ * supports one framebuffer at the moment, so disabling the .init function of PCI driver is
+ * done to make sure of that.
+ */
+static void mainboard_configure_internal_gfx(void *unused)
+{
+ struct device *dev;
+ const struct eeprom_board_settings *board_cfg = get_board_settings();
+ switch (board_cfg->primary_video) {
+ default:
+ case PRIMARY_VIDEO_ASPEED:
+ dev = pcidev_on_root(2, 0);
+ break;
+ case PRIMARY_VIDEO_INTEL:
+ dev = dev_find_device(PCI_VENDOR_ID_ASPEED, PCI_DEVICE_ID_ASPEED_AST2050_VGA, NULL);
+ break;
+ }
+ disable_internal_gfx(dev);
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, mainboard_configure_internal_gfx, NULL)
--
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Hello Subrata Banik, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62645
to look at the new patch set (#6).
Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case
......................................................................
soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
M src/mainboard/google/brya/variants/anahera/overridetree.cb
M src/mainboard/google/brya/variants/anahera4es/overridetree.cb
M src/mainboard/google/brya/variants/banshee/overridetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
M src/mainboard/google/brya/variants/brask/variant.c
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya0/variant.c
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/variant.c
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/felwinter/variant.c
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble/variant.c
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/variant.c
M src/mainboard/google/brya/variants/kano/overridetree.cb
M src/mainboard/google/brya/variants/kano/variant.c
M src/mainboard/google/brya/variants/nereid/overridetree.cb
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
M src/mainboard/google/brya/variants/primus/overridetree.cb
M src/mainboard/google/brya/variants/primus4es/overridetree.cb
M src/mainboard/google/brya/variants/redrix/overridetree.cb
M src/mainboard/google/brya/variants/redrix4es/overridetree.cb
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko4es/overridetree.cb
M src/mainboard/google/brya/variants/taniks/overridetree.cb
M src/mainboard/google/brya/variants/vell/overridetree.cb
M src/mainboard/google/brya/variants/volmar/overridetree.cb
M src/mainboard/google/brya/variants/volmar/variant.c
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/devicetree_n.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/prodrive/atlas/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
41 files changed, 284 insertions(+), 279 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/6
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Change subject: coreboot_tables.c: Expose the ACPI RSDP
......................................................................
Patch Set 4: Code-Review+2
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Change subject: libpayload: Parse the ACPI RSDP table entry
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/62576/comment/de4d8947_437f3333
PS6, Line 271: info->acpi_rsdp = cb_unpack64(cb_acpi_rsdp->rsdp_pointer);
Technically shouldn't there be a virt_to_phys() call after unpacking?
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