coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Krishna P Bhat D (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62358/comment/0e1f147e_391716c5 PS4, Line 9: Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on : ME_RW blobs. : Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B : regions. : On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B : regions. > nit: no line break between sentences. […] Ack File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62358/comment/113d22e0_48a8d94f PS4, Line 89: LZMA > Just curious, have you benchmarked LZ4 here too (both decompression time and compression ratio) ? With LZMA: FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1279068 LZMA (2002944 decompressed) With LZ4: FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1365742 LZ4 (2002944 decompressed) -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:20:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Krishna P Bhat D (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Patrick Rudolph, Reka Norman, Jamie Ryu, Tim Wawrzynczak, Reka Norman, Nick Vaccaro, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62358 to look at the new patch set (#5). Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... soc/intel/common: Add Kconfig to enable compression on ME_RW blobs Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B regions. On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B regions. FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none FMAP REGION: ME_RW_B Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/62358/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa: Add fmd file for nissa
by Krishna P Bhat D (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Rizwan Qureshi. Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62372 to look at the new patch set (#8). Change subject: mb/google/nissa: Add fmd file for nissa ...................................................................... mb/google/nissa: Add fmd file for nissa Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash layout for brya is of 32MB size, and nissa is expected to have 16MB SPI NOR flash. The current composition of AP firmware exceeds 16MB. To get an estimate of the unutilized region in the current flash layout for nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware size to under 16MB and to remove the RW_UNUSED regions from the final fmd file. Below table gives the size reduction from brya fmd to nissa fmd: +----------------+-------------------+---------------+ | Region | Earlier size (KB) | New size (KB) | +================+===================+===============+ | SI_ME | 5116 | 3772 | +----------------+-------------------+---------------+ | RW_SECTION_A/B | 8192 | 4344 | +----------------+-------------------+---------------+ | VBLOCK_A/B | 64 | 8 | +----------------+-------------------+---------------+ | ME_RW_A/B* | 3008 | 1434 | +----------------+-------------------+---------------+ | RW_LEGACY | 2048 | 1024 | +----------------+-------------------+---------------+ | RW_ELOG | 16 | 4 | +----------------+-------------------+---------------+ | SHARED_DATA | 8 | 4 | +----------------+-------------------+---------------+ | VBLOCK_DEV | 8 | 0 | +----------------+-------------------+---------------+ | RW_SPD_CACHE | 4 | 0 | +----------------+-------------------+---------------+ | RW_NVRAM | 24 | 8 | +----------------+-------------------+---------------+ | WP_RO | 8192 | 4096 | +----------------+-------------------+---------------+ | GBB | 448 | 12 | +----------------+-------------------+---------------+ *Based on LZMA compression on ME_RW_A/B regions. With LZMA compression, this region can be 1434K. Without this, ~665K will be more in each of these regions. Patch: https://review.coreboot.org/c/coreboot/+/62358/ BUG=b:202783191 BRANCH=None TEST=Build and boot Nivviks. Cq-Depend: chrome-internal:4584911 Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/chromeos-nissa.fmd 2 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62372/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Gerrit-Change-Number: 62372 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
by Krishna P Bhat D (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Kangheui Won, Rizwan Qureshi, Balaji Manigandan. Hello build bot (Jenkins), Kangheui Won, Tim Wawrzynczak, Reka Norman, Rizwan Qureshi, Balaji Manigandan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62570 to look at the new patch set (#3). Change subject: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig ...................................................................... mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/62570/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Gerrit-Change-Number: 62570 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Yu-Ping Wu, Jianjun Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/e220a00b_a842f9b2 PS9, Line 14: 100ms > Looking at a typical 8195 boot timeline: […] Hmmm, I didn't know about `get_us_since_boot()`. Something to keep in mind is that it only works as expected if `COLLECT_TIMESTAMPS` is enabled, but it's only `default y if ARCH_X86`. I think an implementation of `timestamp_get()` is needed for this to work. We just need to store a timestamp just after asserting PCIe reset somewhere that persists across stages, then read the value and delay (if needed) before de-asserting PCIe reset. This value can be put in the linker script as a symbol and then migrated to CBMEM in romstage using a `CBMEM_INIT` hook. If `COLLECT_TIMESTAMPS` can be used on Mediatek platforms, it already implements a list of timestamps that persists across stages and is available in CBMEM after coreboot is done. Using this, it's just a matter of adding a function to the timestamp.h API to get a timestamp by ID, and make sure timestamps are added with `timestamp_add_now()`. If we assert PCIe reset in bootblock, we can use the `End of bootblock` timestamp to calculate the elapsed time. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:18:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable c1-state auto demotion for Brya & Brask
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Vinay Kumar, Tim Wawrzynczak, Sridhar Siricilla. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62630 ) Change subject: mb/google/brya: Disable c1-state auto demotion for Brya & Brask ...................................................................... Patch Set 7: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62630/comment/2d0996c4_336d66e4 PS5, Line 9: C state > > Done […] Done https://review.coreboot.org/c/coreboot/+/62630/comment/4f51a94f_e3d1c5cc PS5, Line 13: disabling this feature results in 110 mW power savings > > > Yes, no performance impact was seen with disabling autodemotion. […] Yes Subrata, as per my understanding it would not have impact in case of Balanced power/performance policy. Since coreboot uses balanced policy, it's working in our case. @Vinay, Can you help to clarify if my understanding is incorrect? Commit Message: https://review.coreboot.org/c/coreboot/+/62630/comment/272dfc0d_649db983 PS6, Line 7: C > c1 Done https://review.coreboot.org/c/coreboot/+/62630/comment/a6df7419_e494af32 PS6, Line 9: c-state > c1 state Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Gerrit-Change-Number: 62630 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:16:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62629 ) Change subject: soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/62629/comment/396ff58b_b7cc01ab PS4, Line 572: DisableC1StateAutoDemotion > Do you want to put CB:62645 at the top of this patch train? (thanks BTW!!!) Thank you Tim 😊 I have taken that patch as a base for this patchsets. -- To view, visit https://review.coreboot.org/c/coreboot/+/62629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Gerrit-Change-Number: 62629 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Subrata Banik, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62629 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion ...................................................................... soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Check code compiles and correct value has been passed to FSP. Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/62629/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Gerrit-Change-Number: 62629 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Disable c1-state auto demotion for Brya & Brask
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Vinay Kumar, Tim Wawrzynczak. Hello Felix Singer, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62630 to look at the new patch set (#7). Change subject: mb/google/brya: Disable c1-state auto demotion for Brya & Brask ...................................................................... mb/google/brya: Disable c1-state auto demotion for Brya & Brask c1-state auto demotion feature allows hardware to determine c1-state as per platform policy. Since Brya sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results in 110 mW power savings during video playback. BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also power and performance impact has been measure by respective teams. Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62630/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Gerrit-Change-Number: 62630 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Use Kconfigs for Descriptor Region
by Felix Held (Code Review) 07 Mar '22

07 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62264 ) Change subject: soc/intel/alderlake: Use Kconfigs for Descriptor Region ...................................................................... soc/intel/alderlake: Use Kconfigs for Descriptor Region The patch uses Kconfigs for Descriptor Region and Descriptor Region size instead of locally defined macros TEST=Build and boot Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/bootblock/pmc_descriptor.c 1 file changed, 8 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Krishna P Bhat D: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c index 4e80957..c585f70 100644 --- a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c @@ -11,8 +11,6 @@ #include <soc/bootblock.h> #include <types.h> -#define SI_DESC_REGION "SI_DESC" -#define SI_DESC_REGION_SZ 4096 #define PMC_DESC_7_BYTE3 0xc32 /* Flash Master 1 : HOST/BIOS */ @@ -44,18 +42,19 @@ /* It updates PMC Descriptor in the Descriptor Region */ void configure_pmc_descriptor(void) { - uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; struct region_device desc_rdev; if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) return; - if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION); return; } - if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + if (rdev_readat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) != + CONFIG_SI_DESC_REGION_SZ) { printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); return; } @@ -70,13 +69,13 @@ si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; - if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + if (rdev_eraseat(&desc_rdev, 0, CONFIG_SI_DESC_REGION_SZ) != CONFIG_SI_DESC_REGION_SZ) { printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); return; } - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) - != SI_DESC_REGION_SZ) { + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) + != CONFIG_SI_DESC_REGION_SZ) { printk(BIOS_ERR, "Failed to update Descriptor Region\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/62264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa Gerrit-Change-Number: 62264 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022