coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Tim Wawrzynczak, Hima B Chilmakuru. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61722 ) Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 Gerrit-Change-Number: 61722 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 18:15:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: drop orphaned VR domains enum
by Michael Niewöhner (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62622 ) Change subject: soc/intel/tgl: drop orphaned VR domains enum ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > the arrays were dropped in commit bae2d554373baca1023 (which is correct, TGL only has 1 VR domain, V […] Yep, I had to figure that out first, too, since there wasn't much reference in the change :/ Anything to do for me or just a sidenote? -- To view, visit https://review.coreboot.org/c/coreboot/+/62622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Gerrit-Change-Number: 62622 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 18:15:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: add device UART #3 to chipset devicetree
by Michael Niewöhner (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62624 ) Change subject: soc/intel/tgl: add device UART #3 to chipset devicetree ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > does it show up in PCI enumeration? oh... will test later. thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3abccf65d59278b38835cdfda9e54991d6edaacf Gerrit-Change-Number: 62624 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 18:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hima B Chilmakuru. Hello build bot (Jenkins), Subrata Banik, Nick Vaccaro, Hima B Chilmakuru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61722 to look at the new patch set (#11). Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version ...................................................................... mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version cr50 firmware revisions starting at 0.5.5 and later are able to extend their IRQ pulses to be a minimum of 100us long. This change will enable cr50 long interrupt pulses when it detects the feature is supported by the detected firmware version. If the capability was detected, then GPIO PM will be enabled for the device, otherwise it will be disabled. BUG=b:202246591 TEST=boot brya0, check console logs for the correct message, and verify the GPIO PM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/mainboard.c M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 4 files changed, 30 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/61722/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/61722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 Gerrit-Change-Number: 61722 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/tpm/cr50: Add I2C bus support to cr50 driver
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62059 ) Change subject: drivers/tpm/cr50: Add I2C bus support to cr50 driver ...................................................................... drivers/tpm/cr50: Add I2C bus support to cr50 driver This allows mainboards using an I2C bus to communicate with the cr50 to reuse the functionality related to firmware version and BOARD_CFG. BUG=b:202246591 TEST=boot on brya0, see cr50 FW version in logs Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/i2c/tpm/cr50.c M src/drivers/tpm/cr50.c 2 files changed, 37 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 4152852..f8548a7 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -17,14 +17,15 @@ #include <commonlib/endian.h> #include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c_simple.h> +#include <drivers/tpm/cr50.h> +#include <endian.h> +#include <security/tpm/tis.h> #include <string.h> #include <types.h> -#include <delay.h> -#include <console/console.h> -#include <device/i2c_simple.h> -#include <endian.h> #include <timer.h> -#include <security/tpm/tis.h> #include "tpm.h" @@ -126,7 +127,7 @@ * * Returns -1 on error, 0 on success. */ -static int cr50_i2c_write(uint8_t addr, uint8_t *buffer, size_t len) +static int cr50_i2c_write(uint8_t addr, const uint8_t *buffer, size_t len) { if (tpm_dev.addr == 0) return -1; @@ -473,6 +474,7 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) { + struct cr50_firmware_version ver; uint32_t did_vid = 0; if (dev_addr == 0) { @@ -498,6 +500,12 @@ printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", bus, dev_addr, did_vid >> 16); + if (tpm_first_access_this_boot()) { + /* This is called for the side-effect of printing the version string. */ + cr50_get_firmware_version(&ver); + cr50_set_board_cfg(); + } + chip->is_open = 1; return 0; } @@ -505,3 +513,13 @@ void tpm_vendor_cleanup(struct tpm_chip *chip) { } + +cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) +{ + return cr50_i2c_write(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; +} + +cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +{ + return cr50_i2c_read(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; +} diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c index c8ab5e4..4b5e813 100644 --- a/src/drivers/tpm/cr50.c +++ b/src/drivers/tpm/cr50.c @@ -23,6 +23,9 @@ #define CR50_FW_VER_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xf90) #define CR50_BOARD_CFG_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xfe0) +#define CR50_FW_VER_REG_I2C 0x0f +#define CR50_BOARD_CFG_REG_I2C 0x1c + /* Return register address, which depends on the bus type, or -1 for error. */ static int get_reg_addr(enum cr50_register reg) { @@ -37,6 +40,16 @@ } } + if (CONFIG(I2C_TPM)) { + switch (reg) { + case CR50_FW_VER_REG: + return CR50_FW_VER_REG_I2C; + case CR50_BOARD_CFG_REG: + return CR50_BOARD_CFG_REG_I2C; + default: + return -1; + } + } return -1; } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0 Gerrit-Change-Number: 62059 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/tpm/spi: Refactor out some cr50-specific logic
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61977 ) Change subject: drivers/tpm/spi: Refactor out some cr50-specific logic ...................................................................... drivers/tpm/spi: Refactor out some cr50-specific logic Mainboards accessing the cr50 over an I2C bus may want to reuse some of the same firmware version and BOARD_CFG logic, therefore refactor this logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses the new tis_vendor_read/write() functions in order to access the cr50 regardless of the bus which is physically used. In order to leave SPI devices intact, the tis_vendor_* functions are added to the SPI driver. BUG=b:202246591 TEST=boot to OS on google/dratini, see the same FW version and board_cfg console prints as before the change. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/spi/tpm/tpm.c M src/drivers/spi/tpm/tpm.h M src/drivers/tpm/Makefile.inc A src/drivers/tpm/cr50.c A src/drivers/tpm/cr50.h M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/security/tpm/tis.h 8 files changed, 249 insertions(+), 163 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 971e603..53b3a25 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -23,8 +23,6 @@ #include "tpm.h" -#define TPM_LOCALITY_0_SPI_BASE 0x00d40000 - /* Assorted TPM2 registers for interface type FIFO. */ #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) @@ -34,14 +32,6 @@ #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) #define CR50_BOARD_CFG (TPM_LOCALITY_0_SPI_BASE + 0xfe0) -#define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U -#define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU - -#define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U -#define CR50_BOARD_CFG_VALUE \ - (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ - ? CR50_BOARD_CFG_100US_READY_PULSE : 0) - #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ /* SPI slave structure for TPM device. */ @@ -49,7 +39,6 @@ /* Cached TPM device identification. */ static struct tpm2_info tpm_info; -static struct cr50_firmware_version cr50_firmware_version; /* * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of @@ -427,114 +416,12 @@ return CB_ERR; } -static enum cb_err cr50_parse_fw_version(const char *version_str, - struct cr50_firmware_version *ver) -{ - int epoch, major, minor; - - char *number = strstr(version_str, " RW_A:"); - if (!number) - number = strstr(version_str, " RW_B:"); - if (!number) - return CB_ERR_ARG; - number += 6; /* Skip past the colon. */ - - epoch = skip_atoi(&number); - if (*number++ != '.') - return CB_ERR_ARG; - major = skip_atoi(&number); - if (*number++ != '.') - return CB_ERR_ARG; - minor = skip_atoi(&number); - - ver->epoch = epoch; - ver->major = major; - ver->minor = minor; - return CB_SUCCESS; -} - -static bool cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) -{ - /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 - * and onwards. */ - if (version->epoch > 0 || version->major >= 7 - || (version->major >= 5 && version->minor >= 5)) - return true; - printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", - version->epoch, version->major, version->minor); - return false; -} - -/** - * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. - */ -static void cr50_set_board_cfg(void) -{ - uint32_t board_cfg_value; - if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) - return; - /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ - if (tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value)) - != CB_SUCCESS) { - printk(BIOS_INFO, "Error reading from cr50\n"); - return; - } - if ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { - printk(BIOS_INFO, - "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", - board_cfg_value, CR50_BOARD_CFG_VALUE); - return; - } - if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) { - /* The high bit is set, meaning that the Cr50 is already locked on a particular - * value for the register, but not the one we wanted. */ - printk(BIOS_ERR, - "Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", - board_cfg_value, CR50_BOARD_CFG_VALUE); - return; - } - printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", - board_cfg_value, CR50_BOARD_CFG_VALUE); - board_cfg_value = CR50_BOARD_CFG_VALUE; - if (tpm2_write_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value)) - != CB_SUCCESS) - printk(BIOS_INFO, "Error writing to cr50\n"); -} - -/* - * Expose method to read the CR50_BOARD_CFG register, will return zero if - * register not supported by Cr50 firmware. - */ -static uint32_t cr50_get_board_cfg(void) -{ - uint32_t board_cfg_value; - if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) - return 0; - - if (tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value)) - != CB_SUCCESS) { - printk(BIOS_INFO, "Error reading from cr50\n"); - return 0; - } - return board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK; -} - -bool cr50_is_long_interrupt_pulse_enabled(void) -{ - return cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE; -} - /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { 0x00281ae0, /* H1 based Cr50 security chip. */ 0x0000104a /* ST33HTPH2E32 */ }; -static bool first_access_this_boot(void) -{ - return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); -} - int tpm2_init(struct spi_slave *spi_if) { uint32_t did_vid, status; @@ -579,7 +466,7 @@ printk(BIOS_INFO, " done!\n"); // FIXME: Move this to tpm_setup() - if (first_access_this_boot()) + if (tpm_first_access_this_boot()) /* * Claim locality 0, do it only during the first * initialization after reset. @@ -609,40 +496,15 @@ printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); - /* Let's report device FW version if available. */ + /* Do some cr50-specific things here. */ if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) { - int chunk_count = 0; - size_t chunk_size = 50; - char version_str[301]; + struct cr50_firmware_version ver; - /* - * Does not really matter what's written, this just makes sure - * the version is reported from the beginning. - */ - tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); - - /* - * Read chunk_size bytes at a time, last chunk will be zero padded. - */ - do { - tpm2_read_reg(TPM_FW_VER, - version_str + chunk_count * chunk_size, - chunk_size); - if (!version_str[++chunk_count * chunk_size - 1]) - /* Zero padding detected: end of string. */ - break; - /* Check if there is enough room for reading one more chunk. */ - } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); - version_str[chunk_count * chunk_size] = '\0'; - printk(BIOS_INFO, "Firmware version: %s\n", version_str); - - if (cr50_parse_fw_version(version_str, &cr50_firmware_version) != CB_SUCCESS) { - printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); - return -1; - } - if (CR50_BOARD_CFG_VALUE) { - if (first_access_this_boot()) - cr50_set_board_cfg(); + if (tpm_first_access_this_boot()) { + /* This is called for the side-effect of printing the firmware version + string */ + cr50_get_firmware_version(&ver); + cr50_set_board_cfg(); } } return 0; @@ -866,7 +728,12 @@ return payload_size; } -void cr50_get_firmware_version(struct cr50_firmware_version *version) +cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) { - memcpy(version, &cr50_firmware_version, sizeof(*version)); + return tpm2_write_reg(addr, buffer, bytes); +} + +cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +{ + return tpm2_read_reg(addr, buffer, bytes); } diff --git a/src/drivers/spi/tpm/tpm.h b/src/drivers/spi/tpm/tpm.h index f48943e..cb09148 100644 --- a/src/drivers/spi/tpm/tpm.h +++ b/src/drivers/spi/tpm/tpm.h @@ -3,9 +3,12 @@ #ifndef __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H #define __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H +#include <drivers/tpm/cr50.h> #include <stddef.h> #include <spi-generic.h> +#define TPM_LOCALITY_0_SPI_BASE 0x00d40000 + /* * A tpm device descriptor, values read from the appropriate device regisrers * are cached here. @@ -16,13 +19,6 @@ uint16_t revision; }; -/* Structure describing the elements of Cr50 firmware version. */ -struct cr50_firmware_version { - int epoch; - int major; - int minor; -}; - /* * Initialize a TPM2 device: read its id, claim locality of zero, verify that * this indeed is a TPM2 device. Use the passed in handle to access the right @@ -47,10 +43,4 @@ /* Get information about previously initialized TPM device. */ void tpm2_get_info(struct tpm2_info *info); -/* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ -bool cr50_is_long_interrupt_pulse_enabled(void); - -/* Get the cr50 firmware version information. */ -void cr50_get_firmware_version(struct cr50_firmware_version *version); - #endif /* ! __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H */ diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 9833eb4..a56c02b 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -5,3 +5,9 @@ else ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c endif + +bootblock-$(CONFIG_TPM_CR50) += cr50.c +verstage-$(CONFIG_TPM_CR50) += cr50.c +romstage-$(CONFIG_TPM_CR50) += cr50.c +ramstage-$(CONFIG_TPM_CR50) += cr50.c +postcar-$(CONFIG_TPM_CR50) += cr50.c diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c new file mode 100644 index 0000000..c8ab5e4 --- /dev/null +++ b/src/drivers/tpm/cr50.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include <drivers/spi/tpm/tpm.h> +#include <security/tpm/tis.h> +#include <string.h> +#include <types.h> + +#define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U +#define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU + +#define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U +#define CR50_BOARD_CFG_VALUE \ + (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ + ? CR50_BOARD_CFG_100US_READY_PULSE : 0) + +static struct cr50_firmware_version cr50_firmware_version; + +enum cr50_register { + CR50_FW_VER_REG, + CR50_BOARD_CFG_REG, +}; + +#define CR50_FW_VER_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xf90) +#define CR50_BOARD_CFG_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xfe0) + +/* Return register address, which depends on the bus type, or -1 for error. */ +static int get_reg_addr(enum cr50_register reg) +{ + if (CONFIG(SPI_TPM)) { + switch (reg) { + case CR50_FW_VER_REG: + return CR50_FW_VER_REG_SPI; + case CR50_BOARD_CFG_REG: + return CR50_BOARD_CFG_REG_SPI; + default: + return -1; + } + } + + + return -1; +} + +static bool cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) +{ + /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 + * and onwards. */ + if (version->epoch > 0 || version->major >= 7 + || (version->major >= 5 && version->minor >= 5)) + return true; + + printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", + version->epoch, version->major, version->minor); + + return false; +} + +/* + * Expose method to read the CR50_BOARD_CFG register, will return zero if + * register not supported by Cr50 firmware. + */ +static uint32_t cr50_get_board_cfg(void) +{ + uint32_t value; + + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return 0; + + const cb_err_t ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, + sizeof(value)); + if (ret != CB_SUCCESS) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return 0; + } + + return value & CR50_BOARD_CFG_FEATUREBITS_MASK; +} + +/** + * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. + */ +cb_err_t cr50_set_board_cfg(void) +{ + uint32_t value; + cb_err_t ret; + + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return CB_ERR; + + /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ + ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); + if (ret != CB_SUCCESS) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return CB_ERR; + } + + if ((value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { + printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", + value, CR50_BOARD_CFG_VALUE); + return CB_SUCCESS; + } + + if (value & CR50_BOARD_CFG_LOCKBIT_MASK) { + /* The high bit is set, meaning that the Cr50 is already locked on a particular + * value for the register, but not the one we wanted. */ + printk(BIOS_ERR, "Current CR50_BOARD_CFG = 0x%08x, does not match" + "desired = 0x%08x\n", value, CR50_BOARD_CFG_VALUE); + return CB_ERR; + } + + printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", + value, CR50_BOARD_CFG_VALUE); + value = CR50_BOARD_CFG_VALUE; + + ret = tis_vendor_write(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); + if (ret != CB_SUCCESS) { + printk(BIOS_ERR, "Error writing to cr50\n"); + return ret; + } + + return CB_SUCCESS; +} + +bool cr50_is_long_interrupt_pulse_enabled(void) +{ + return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); +} + +static cb_err_t cr50_parse_fw_version(const char *version_str, + struct cr50_firmware_version *ver) +{ + int epoch, major, minor; + + char *number = strstr(version_str, " RW_A:"); + if (!number) + number = strstr(version_str, " RW_B:"); + if (!number) + return CB_ERR_ARG; + number += 6; /* Skip past the colon. */ + + epoch = skip_atoi(&number); + if (*number++ != '.') + return CB_ERR_ARG; + major = skip_atoi(&number); + if (*number++ != '.') + return CB_ERR_ARG; + minor = skip_atoi(&number); + + ver->epoch = epoch; + ver->major = major; + ver->minor = minor; + return CB_SUCCESS; +} + +cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version) +{ + if (cr50_firmware_version.epoch || cr50_firmware_version.major || + cr50_firmware_version.minor) + goto success; + + int chunk_count = 0; + size_t chunk_size = 50; + char version_str[301]; + int addr = get_reg_addr(CR50_FW_VER_REG); + + /* + * Does not really matter what's written, this just makes sure + * the version is reported from the beginning. + */ + tis_vendor_write(addr, &chunk_size, 1); + + /* + * Read chunk_size bytes at a time, last chunk will be zero padded. + */ + do { + uint8_t *buf = (uint8_t *)version_str + chunk_count * chunk_size; + tis_vendor_read(addr, buf, chunk_size); + if (!version_str[++chunk_count * chunk_size - 1]) + /* Zero padding detected: end of string. */ + break; + /* Check if there is enough room for reading one more chunk. */ + } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); + + version_str[chunk_count * chunk_size] = '\0'; + printk(BIOS_INFO, "Firmware version: %s\n", version_str); + + if (cr50_parse_fw_version(version_str, &cr50_firmware_version) != CB_SUCCESS) { + printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); + return CB_ERR; + } + +success: + *version = cr50_firmware_version; + return CB_SUCCESS; +} diff --git a/src/drivers/tpm/cr50.h b/src/drivers/tpm/cr50.h new file mode 100644 index 0000000..4fdd06b --- /dev/null +++ b/src/drivers/tpm/cr50.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRIVERS_TPM_CR50_H__ +#define __DRIVERS_TPM_CR50_H__ + +#include <types.h> + +/* Structure describing the elements of Cr50 firmware version. */ +struct cr50_firmware_version { + int epoch; + int major; + int minor; +}; + +/* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ +bool cr50_is_long_interrupt_pulse_enabled(void); + +/* Get the Cr50 firmware version information. */ +cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version); + +/* Set the BOARD_CFG register depending on Cr50 Kconfigs */ +cb_err_t cr50_set_board_cfg(void); + +#endif /* __DRIVERS_TPM_CR50_H__ */ diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 700b3e3..ca5a21c 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> -#include <drivers/spi/tpm/tpm.h> +#include <drivers/tpm/cr50.h> #include <ec/ec.h> #include <security/tpm/tss.h> #include <soc/soc_chip.h> diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 95b9ce7..7089ddd 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -3,7 +3,7 @@ #include <console/console.h> #include <baseboard/variants.h> #include <device/device.h> -#include <drivers/spi/tpm/tpm.h> +#include <drivers/tpm/cr50.h> #include <ec/ec.h> #include <fw_config.h> #include <gpio.h> diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index 3b65134..0ef5a8a 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -111,5 +111,9 @@ */ cb_err_t tis_vendor_read(unsigned int addr, void *recvbuf, size_t recv_size); +static inline bool tpm_first_access_this_boot(void) +{ + return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); +} #endif /* TIS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Gerrit-Change-Number: 61977 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
by Selma Bensaid (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Bora Guvendik, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Julius Werner, Patrick Rudolph. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 ) Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 17: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 17 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 18:01:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Lean Sheng Tan (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/62566/comment/04de3ba4_405ea25e PS2, Line 164: MP_SERVICES_PPI > At least what I have heared from Sheng Alder Lake is affected, too. Yeah sorry for late reply. I also observed the same thing from my side. I checked the MTRR output by coreboot where the memory for SPI was not there (maybe i missed some config?) and there was always some slow moment before entering to payload. With this changes it is resolved. Already asked Intel ADL team to help verify on their side. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:57:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/tpm/spi: Refactor out some cr50-specific logic
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Tim Wawrzynczak, Christian Walter, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61977 ) Change subject: drivers/tpm/spi: Refactor out some cr50-specific logic ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Gerrit-Change-Number: 61977 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 17:53:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taniks: Add GL9750 SD card reader support
by Felix Held (Code Review) 07 Mar '22

07 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62588 ) Change subject: mb/google/brya/var/taniks: Add GL9750 SD card reader support ...................................................................... mb/google/brya/var/taniks: Add GL9750 SD card reader support Add GL9750 SD card reader support. BUG=b:222402409 TEST=Build FW and check device function normally. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index f88f429..3895aab 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -148,6 +148,7 @@ bool "-> Taniks" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E config BOARD_GOOGLE_VELL -- To view, visit https://review.coreboot.org/c/coreboot/+/62588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a Gerrit-Change-Number: 62588 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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