coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... Patch Set 4: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62358/comment/12b2465d_c8fd6655 PS4, Line 9: Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on : ME_RW blobs. : Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B : regions. : On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B : regions. nit: no line break between sentences. If they are new paragraphs, include a blank line in-between, otherwise let them flow one after the other. File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62358/comment/be03d291_d8b91137 PS4, Line 89: LZMA Just curious, have you benchmarked LZ4 here too (both decompression time and compression ratio) ? -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:14:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Hung-Te Lin (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/b9997fa4_180a7f1b PS9, Line 14: 100ms > Is there a way to ensure this minimum delay of 100ms is still met? coreboot could be too fast in som […] Agree with Angel's concern. When will we do next init? In ramstage? Although the romstage is usually longer than 100ms, I wonder if we can create some timestamp, and verify that in next init, and to do extra delay if it hasn't meet 100ms. File src/soc/mediatek/mt8195/bootblock.c: https://review.coreboot.org/c/coreboot/+/62359/comment/8077e745_7996a4a6 PS9, Line 18: : if (CONFIG(PCI)) : mtk_pcie_pre_init(); I wonder if we can move this to bootblock_mainboard_init -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:10:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: add device UART #3 to chipset devicetree
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62624 ) Change subject: soc/intel/tgl: add device UART #3 to chipset devicetree ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: > I'm not convinced that this device actually exists. My -1 is because uart. […] does it show up in PCI enumeration? PS2: I'm not eit -- To view, visit https://review.coreboot.org/c/coreboot/+/62624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3abccf65d59278b38835cdfda9e54991d6edaacf Gerrit-Change-Number: 62624 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:09:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Nico Huber, Jakub Czapiga, Tim Wawrzynczak, Julius Werner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62573 ) Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... Patch Set 4: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/62573/comment/e101925a_f679d7a9 PS4, Line 587: }; > Looks like we forgot to remove it in libpayload, I'll move the comment there. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jakub Czapiga, Patrick Rudolph, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62181 ) Change subject: src/device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62181/comment/01d90110_0ff83748 PS4, Line 9: While on it, fix SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM and SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM values : respectively to 0x08 and 0x09. Please do this in a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/62181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Gerrit-Change-Number: 62181 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:06:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 11: Code-Review+1 (1 comment) File src/soc/mediatek/mt8186/spi.c: https://review.coreboot.org/c/coreboot/+/62472/comment/67d61ea0_2b36fdc8 PS11, Line 154: NOR_PIN_DRIVE_STRENGTH I'd drop this `NOR_PIN_DRIVE_STRENGTH` macro and use `GPIO_DRV_8_MA` directly -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:04:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: chipset devicetree: correct TraceHub device alias
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62623 ) Change subject: soc/intel/tgl: chipset devicetree: correct TraceHub device alias ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: maybe consider dropping the TraceHubMode from TGL chip.h then in fsp_params.c just rely on the state of the device to set the UPD? -- To view, visit https://review.coreboot.org/c/coreboot/+/62623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8 Gerrit-Change-Number: 62623 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/mt8186/gpio.c: https://review.coreboot.org/c/coreboot/+/62471/comment/57e6778c_0f5ea19e PS9, Line 203: { 0, 0, 0, } > Done It's possible to omit these lines, the default value is already 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:02:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: chipset devicetree: correct TraceHub device alias
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62623 ) Change subject: soc/intel/tgl: chipset devicetree: correct TraceHub device alias ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8 Gerrit-Change-Number: 62623 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:02:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62645 ) Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... Patch Set 4: (5 comments) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62645/comment/fb841449_27fead4c PS3, Line 76: > can you please align this tab too ? Done File src/mainboard/google/brya/variants/brya4es/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62645/comment/20760f15_6b8d6581 PS3, Line 38: SaGv > Did you miss this ? Ack File src/mainboard/google/brya/variants/gimble/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62645/comment/c3198a59_29390469 PS3, Line 24: SaGv > same Done File src/mainboard/google/brya/variants/taniks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62645/comment/ce9af260_77d99105 PS3, Line 54: SaGv > same Done File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/62645/comment/d1e5806b_2972f5d7 PS3, Line 230: SaGv > please fix this as well Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:57:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022