coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and ...
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Selma Bensaid, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61887 ) Change subject: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Gerrit-Change-Number: 61887 Gerrit-PatchSet: 15 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:47:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apollolake: Hook up CnviMode to DeviceTree
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Andrey Petrov, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62127 ) Change subject: soc/apollolake: Hook up CnviMode to DeviceTree ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62127/comment/325dd8e7_7d810728 PS3, Line 7: DeviceTree nit: coreboot's devicetree is spelled in lowercase -- To view, visit https://review.coreboot.org/c/coreboot/+/62127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Gerrit-Change-Number: 62127 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Correct Keyboard Backlight offsets for GLK
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62126 ) Change subject: ec/starlabs: Correct Keyboard Backlight offsets for GLK ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23bac43301635e6b18f1cbd28311e7210b049c70 Gerrit-Change-Number: 62126 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:46:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Guard Max Charge in Kconfig
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62123 ) Change subject: ec/starlabs: Guard Max Charge in Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a Gerrit-Change-Number: 62123 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:45:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 98: (1 comment) File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/58428/comment/70938d8a_4e410231 PS95, Line 19: EC_STARLABS_FAN > Already selected through `BOARD_STARLABS_LABTOP_SERIES`, looks like TGL also has this redundancy. […] Remove as all boards in the series will use a fan. -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 98 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:45:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Remove duplicate value from Kconfig
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62124 ) Change subject: mb/starlabs/labtop: Remove duplicate value from Kconfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0324747f936be27ee39e586124005530d5c424b7 Gerrit-Change-Number: 62124 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:45:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/lite: Add StarLite Mk II
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62646 ) Change subject: mb/starlabs/lite: Add StarLite Mk II ...................................................................... mb/starlabs/lite: Add StarLite Mk II Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8e9b4d97a4799f58ffaf9f15554f45d6f7e12110 --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/lite_apl.md M src/mainboard/starlabs/lite/Kconfig M src/mainboard/starlabs/lite/Kconfig.name A src/mainboard/starlabs/lite/variants/apl/Makefile.inc A src/mainboard/starlabs/lite/variants/apl/devicetree.cb A src/mainboard/starlabs/lite/variants/apl/gpio.c A src/mainboard/starlabs/lite/variants/apl/romstage.c 8 files changed, 694 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/62646/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 02383c9..63a6359 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -180,6 +180,7 @@ ## Star Labs Systems +- [StarLite Mk II](starlabs/lite_apl.md) - [StarLite Mk III](starlabs/lite_glk.md) - [StarBook Mk V](starlabs/starbook_tgl.md) diff --git a/Documentation/mainboard/starlabs/lite_apl.md b/Documentation/mainboard/starlabs/lite_apl.md new file mode 100644 index 0000000..29449ad --- /dev/null +++ b/Documentation/mainboard/starlabs/lite_apl.md @@ -0,0 +1,82 @@ +# StarLite Mk III + +## Specs +- CPU (full processor specs available at https://ark.intel.com) + - Intel N4200 (Apollo Lake) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel HD Graphics 505 + - GOP driver is recommended, VBT is provided + - eDP 11.6-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 8GB on-board +- Networking + - 3165 CNVi WiFi / Bluetooth soldered to PCBA +- Sound + - Realtek ALC269 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 SATA SSD + - RTS5129 MicroSD card reader +- USB + - 640x480 CCD camera + - USB 3.1 Gen 1 Type-C (left) + - USB 3.1 Gen 1 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Trusted Execution Engine firmware (cse_image.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_apl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Gigadevice | ++---------------------+------------+ +| Model | GD25LQ64(B)| ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ + +Please see [here](../common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig index de2e8e1..b140b76 100644 --- a/src/mainboard/starlabs/lite/Kconfig +++ b/src/mainboard/starlabs/lite/Kconfig @@ -18,6 +18,10 @@ select SPI_FLASH_GIGADEVICE select SYSTEM_TYPE_LAPTOP +config BOARD_STARLABS_LITE_APL + select BOARD_STARLABS_LITE_SERIES + select SOC_INTEL_APOLLOLAKE + config BOARD_STARLABS_LITE_GLK select BOARD_STARLABS_LITE_SERIES select EC_STARLABS_KBL_LEVELS @@ -32,7 +36,8 @@ default 0x26 config EC_VARIANT_DIR - default "glk" + default "apl" if BOARD_STARLABS_LITE_APL + default "glk" if BOARD_STARLABS_LITE_GLK config FMDFILE default "src/mainboard/starlabs/lite/board.fmd" @@ -42,10 +47,12 @@ config MAINBOARD_FAMILY string - default "I3" + default "I2" if BOARD_STARLABS_LITE_APL + default "I3" if BOARD_STARLABS_LITE_GLK config MAINBOARD_PART_NUMBER - default "Lite Mk III" + default "Lite Mk II" if BOARD_STARLABS_LITE_APL + default "Lite Mk III" if BOARD_STARLABS_LITE_GLK config MAINBOARD_SMBIOS_PRODUCT_NAME string diff --git a/src/mainboard/starlabs/lite/Kconfig.name b/src/mainboard/starlabs/lite/Kconfig.name index 7cfb612..8b2fb0f 100644 --- a/src/mainboard/starlabs/lite/Kconfig.name +++ b/src/mainboard/starlabs/lite/Kconfig.name @@ -1,4 +1,7 @@ comment "Star Labs Lite Series" +config BOARD_STARLABS_LITE_APL + bool "Star Labs Lite Mk II (N4200)" + config BOARD_STARLABS_LITE_GLK bool "Star Labs Lite Mk III (N5000)" diff --git a/src/mainboard/starlabs/lite/variants/apl/Makefile.inc b/src/mainboard/starlabs/lite/variants/apl/Makefile.inc new file mode 100644 index 0000000..05b0677 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/lite/variants/apl/devicetree.cb b/src/mainboard/starlabs/lite/variants/apl/devicetree.cb new file mode 100644 index 0000000..9fbecad --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/devicetree.cb @@ -0,0 +1,160 @@ +chip soc/intel/apollolake + device cpu_cluster 0 on + device lapic 0 on end + end + + # Graphics + # TODO: + # register "panel_cfg" = "{ + # .up_delay_ms = 0, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 0, // T9 + # .down_delay_ms = 0, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM + # }" + +# PM Util (soc/intel/apollolake/pmutil.c) + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | + LPC_IOE_EC_62_66 | + LPC_IOE_KBC_60_64" + + register "dptf_enable" = "0" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + register "pnp_settings" = "PNP_PERF_POWER" + + register "ModPhyIfValue" = "0x12" + + register "usb_config_override" = "1" + register "DisableComplianceMode" = "1" + + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + register "pcie_rp_deemphasis_enable[0]" = "1" + register "pcie_rp_deemphasis_enable[1]" = "1" + register "pcie_rp_deemphasis_enable[2]" = "1" + register "pcie_rp_deemphasis_enable[3]" = "1" + register "pcie_rp_deemphasis_enable[4]" = "1" + register "pcie_rp_deemphasis_enable[5]" = "1" + + # GPE configuration + register "gpe0_dw1" = "PMC_GPE_NW_63_32" + register "gpe0_dw2" = "PMC_GPE_N_95_64" + register "gpe0_dw3" = "PMC_GPE_NW_31_0" + + register "slp_s3_assertion_width_usecs" = "50000" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # Gen + device pci 03.0 off end # Iunit + device pci 0c.0 on # CNVi + chip drivers/wifi/generic + register "wake" = "GPE0A_CNVI_PME_STS" + device generic 0 on end + end + end + device pci 0d.0 off end # P2SB + device pci 0d.1 hidden end # PMC + device pci 0d.2 on end # SPI + device pci 0d.3 off end # Shared SRAM + device pci 0e.0 on # Audio + subsystemid 0x10ec 0x111e + end + device pci 0f.0 on end # Heci1 + device pci 0f.1 on end # Heci2 + device pci 0f.2 on end # Heci3 + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 off end # PCIe-A 0 Slot 1 + device pci 13.1 off end # PCIe-A 1 + device pci 13.2 off end # PCIe-A 2 Onboard Lan + device pci 13.3 off end # PCIe-A 3 + device pci 14.0 off end # PCIe-B 0 Slot2 + device pci 14.1 off end # PCIe-B 1 Onboard M2 Slot(Wifi/BT) + device pci 15.0 on # XHCI + ### USB 2.0 Devices + # Motherboard USB Type C + register "usb2_port[0]" = "PORT_EN(OC0)" + # Motherboard USB 3.0 + register "usb2_port[3]" = "PORT_EN(OC0)" + # Internal Webcam + register "usb2_port[4]" = "PORT_EN(OC0)" + # Daughterboard USB 3.0 + register "usb2_port[5]" = "PORT_EN(OC0)" + # Daughterboard SD Card + register "usb2_port[6]" = "PORT_EN(OC0)" + + ### USB 3.0 Devices + # Motherboard USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + # Motherboard USB Type C + register "usb3_port[1]" = "PORT_EN(OC0)" + # Daughterboard USB 3.0 + register "usb3_port[2]" = "PORT_EN(OC0)" + end device pci 15.1 off end # XDCI + device pci 16.0 off end # I2C0 + device pci 16.1 off end # I2C1 + device pci 16.2 off end # I2C2 + device pci 16.3 off end # I2C3 + device pci 17.0 on end # I2C4 + device pci 17.1 off end # I2C5 + device pci 17.2 off end # I2C6 + device pci 17.3 on # I2C7 + # Handled by touchpad.asl + end + device pci 18.0 on end # UART #0 + device pci 18.1 off end # UART #1 + device pci 18.2 on end # UART #2 + device pci 18.3 off end # UART #3 + device pci 19.0 off end # SPI #0 + device pci 19.1 off end # SPI #1 + device pci 19.2 on end # SPI #2 + device pci 1a.0 off end # PWM + device pci 1b.0 off end # SDCard + device pci 1c.0 off end # eMMC + device pci 1e.0 off end # SDIO + device pci 1f.0 on # LPC Interface + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device pci 1f.1 off end # SMBus + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/starlabs/lite/variants/apl/gpio.c b/src/mainboard/starlabs/lite/variants/apl/gpio.c new file mode 100644 index 0000000..d2533c3 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/gpio.c @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> +#include <variants.h> +#include <types.h> + +/* Early pad configuration in bootblock. */ +const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ----- GPIO Community North ----- */ + + /* ------- GPIO Group North ------- */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_0, DN_20K, PWROK, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_1, DN_20K, PWROK, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_2, DN_20K, PWROK, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_3, DN_20K, PWROK, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_4, DN_20K, PWROK, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_5, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_6, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_7, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_8, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_9, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_10, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_11, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE)), + PAD_CFG_TERM_GPO(GPIO_13, 0, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_14, 1, UP_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_15, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_16, 1, UP_20K, DEEP), + _PAD_CFG_STRUCT(GPIO_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_18, NONE, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_TERM_GPO(GPIO_19, 1, UP_20K, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPIO_20, UP_20K, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE)), + _PAD_CFG_STRUCT(GPIO_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)), + _PAD_CFG_STRUCT(GPIO_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_24, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + PAD_CFG_TERM_GPO(GPIO_25, 1, UP_20K, DEEP), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_26, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_27, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_28, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_29, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_31, NONE, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_32, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_APIC_IOS(GPIO_33, DN_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), + PAD_CFG_TERM_GPO(GPIO_34, 1, DN_20K, DEEP), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_35, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_36, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_TERM_GPO(GPIO_37, 1, DN_20K, DEEP), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_38, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(GPIO_40, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_41, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_43, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_45, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_46, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_47, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_62, 1, DEEP, DN_20K, HIZCRx0, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_63, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_64, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_65, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_66, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_68, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_69, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_70, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_73, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(TCK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(TRST_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(TMS, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(TDI, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(CX_PMODE, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(CX_PREQ_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(JTAGX, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(CX_PRDY_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(TDO, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_RSP, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_RGI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI), + /* CNV_RGI_RSP - RESERVED */ + _PAD_CFG_STRUCT(SVID0_ALERT_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(SVID0_DATA, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(SVID0_CLK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* --- GPIO Community NorthWest --- */ + + /* ----- GPIO Group NorthWest ----- */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_187, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_188, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_189, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_2K)), + _PAD_CFG_STRUCT(GPIO_190, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_2K)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_191, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_192, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_193, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), + _PAD_CFG_STRUCT(GPIO_194, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), + _PAD_CFG_STRUCT(GPIO_195, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), + PAD_CFG_TERM_GPO(GPIO_196, 0, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_197, 0, DN_20K, DEEP), + _PAD_CFG_STRUCT(GPIO_198, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPIO_199, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(GPIO_200, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_201, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_202, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_203, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_204, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMC_SPI_FS0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(PMC_SPI_FS1, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), + _PAD_CFG_STRUCT(PMC_SPI_FS2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(PMC_SPI_RXD, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(PMC_SPI_TXD, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(PMC_SPI_CLK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + PAD_CFG_TERM_GPO(PMIC_PWRGOOD, 1, UP_1K, DEEP), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_RESET_B, NONE, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_213, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_214, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_215, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K)), + PAD_CFG_TERM_GPO(PMIC_STDBY, 1, DN_20K, DEEP), + _PAD_CFG_STRUCT(PROCHOT_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + /* PMIC_I2C_SCL - RESERVED */ + /* PMIC_I2C_SDA - RESERVED */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_74, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_75, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_76, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_77, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_78, 1, DEEP, DN_20K, HIZCRx0, DISPUPD), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_79, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_80, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_81, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_82, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_83, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_84, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_85, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_86, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_87, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_88, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_89, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_90, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_91, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_92, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_97, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_98, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_99, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_100, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_101, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_102, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_103, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(FST_SPI_CLK_FB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_104, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_105, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPIO_106, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_109, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_110, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPIO_111, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPIO_112, 1, DN_20K, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPIO_113, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_116, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_TERM_GPO(GPIO_117, 1, DN_20K, DEEP), + _PAD_CFG_STRUCT(GPIO_118, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPIO_119, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_120, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_121, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPIO_122, UP_20K, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPIO_123, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + + /* ------ GPIO Community West ----- */ + + /* -------- GPIO Group West ------- */ + _PAD_CFG_STRUCT(GPIO_124, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_125, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_126, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_127, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_128, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_129, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_130, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_131, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_132, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_133, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_134, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_2K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_135, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_2K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_136, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_137, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_138, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_139, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), + _PAD_CFG_STRUCT(GPIO_146, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_147, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_148, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_149, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_OWN(GPIO_150, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPIO_151, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_152, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_153, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_154, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_155, 0, DN_20K, DEEP), + _PAD_CFG_STRUCT(GPIO_209, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_210, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPIO_211, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPIO_212, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(OSC_CLK_OUT_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(OSC_CLK_OUT_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(OSC_CLK_OUT_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(OSC_CLK_OUT_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(OSC_CLK_OUT_4, DN_20K, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(PMU_AC_PRESENT, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_BATLOW_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_PLTRST_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_PWRBTN_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_SLP_S0_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_SLP_S3_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_SLP_S4_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(PMU_SUSCLK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 1, DEEP, UP_20K, IGNORE, SAME), + _PAD_CFG_STRUCT(SUS_STAT_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(SUSPWRDNACK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + + /* --- GPIO Community SouthWest --- */ + + /* ----- GPIO Group SouthWest ----- */ + _PAD_CFG_STRUCT(GPIO_205, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_206, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_207, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_208, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(GPIO_156, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), + _PAD_CFG_STRUCT(GPIO_157, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_158, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_159, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_160, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_161, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_162, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_163, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_164, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_165, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_166, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_167, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_168, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_169, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_170, DN_20K, DEEP, OFF, IGNORE, ACPI), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_171, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_172, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(GPIO_179, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPIO_173, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(GPIO_174, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_175, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1)), + _PAD_CFG_STRUCT(GPIO_176, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, NONE, DEEP, EDGE_BOTH, TxDRxE, ACPI), + _PAD_CFG_STRUCT(GPIO_178, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_186, DN_20K, DEEP, OFF, IGNORE, ACPI), + _PAD_CFG_STRUCT(GPIO_182, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)), + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), + _PAD_CFG_STRUCT(SMB_ALERTB, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(SMB_CLK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(SMB_DATA, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + _PAD_CFG_STRUCT(LPC_CLKOUT0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_CLKOUT1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_AD0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_AD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_AD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_AD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_CLKRUNB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), + _PAD_CFG_STRUCT(LPC_FRAMEB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), +}; + +#endif /* CFG_GPIO_H */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/lite/variants/apl/romstage.c b/src/mainboard/starlabs/lite/variants/apl/romstage.c new file mode 100644 index 0000000..79a2a1c --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/apl/romstage.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> + +static const struct lpddr4_sku skus[] = { + [0] = { + .speed = LP4_SPEED_1600, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "D9SKJ", + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), +}; + +static const uint8_t ch0_bit_swizzling[] = { + 0x11, 0x16, 0x13, 0x14, 0x15, 0x10, 0x12, 0x17, + 0x08, 0x0A, 0x0F, 0x0C, 0x09, 0x0D, 0x0B, 0x0E, + 0x01, 0x06, 0x07, 0x05, 0x00, 0x03, 0x02, 0x04, + 0x18, 0x1F, 0x19, 0x1D, 0x1E, 0x1B, 0x1A, 0x1C +}; + +static const uint8_t ch1_bit_swizzling[] = { + 0x05, 0x06, 0x01, 0x00, 0x02, 0x04, 0x03, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0D, 0x0C, 0x0E, 0x0F, + 0x10, 0x14, 0x17, 0x12, 0x16, 0x13, 0x11, 0x15, + 0x1A, 0x18, 0x1F, 0x1B, 0x1C, 0x1D, 0x1E, 0x19 +}; + +static const uint8_t ch2_bit_swizzling[] = { + 0x00, 0x0E, 0x0F, 0x09, 0x0A, 0x0B, 0x0C, 0x08, + 0x16, 0x15, 0x17, 0x11, 0x10, 0x14, 0x13, 0x12, + 0x02, 0x07, 0x05, 0x01, 0x06, 0x04, 0x00, 0x03, + 0x1F, 0x1A, 0x1B, 0x1D, 0x18, 0x19, 0x1C, 0x1E +}; + +static const uint8_t ch3_bit_swizzling[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x06, 0x05, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x12, 0x11, 0x14, 0x16, 0x13, 0x15, 0x10, 0x17, + 0x18, 0x1A, 0x1D, 0x1C, 0x1B, 0x1F, 0x1E, 0x19 +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *config = &memupd->FspmConfig; + + config->Package = 0x01, + config->Profile = 0x05, + config->MemoryDown = 0x01, + config->DDR3LPageSize = 0x01, + config->DDR3LASR = 0x00, + config->ScramblerSupport = 0x01, + config->ChannelHashMask = 0x00, + config->SliceHashMask = 0x00, + config->InterleavedMode = 0x00, + config->ChannelsSlicesEnable = 0x00, + config->MinRefRate2xEnable = 0x00, + config->DualRankSupportEnable = 0x00, + config->RmtMode = 0x00, + config->MemorySizeLimit = 0x00, + config->LowMemoryMaxValue = 0x00, + config->DisableFastBoot = 0x00, + config->HighMemoryMaxValue = 0x00, + config->DIMM0SPDAddress = 0x00, + config->DIMM1SPDAddress = 0x00, + + config->Ch0_RankEnable = 0x03, + config->Ch0_DeviceWidth = 0x02, + config->Ch0_DramDensity = 0x02, + config->Ch0_Option = 0x03, + config->Ch0_OdtConfig = 0x02, + config->Ch0_TristateClk1 = 0x00, + config->Ch0_Mode2N = 0x00, + config->Ch0_OdtLevels = 0x00, + + config->Ch1_RankEnable = 0x03, + config->Ch1_DeviceWidth = 0x02, + config->Ch1_DramDensity = 0x02, + config->Ch1_Option = 0x03, + config->Ch1_OdtConfig = 0x02, + config->Ch1_TristateClk1 = 0x00, + config->Ch1_Mode2N = 0x00, + config->Ch1_OdtLevels = 0x00, + + config->Ch2_RankEnable = 0x03, + config->Ch2_DeviceWidth = 0x02, + config->Ch2_DramDensity = 0x02, + config->Ch2_Option = 0x03, + config->Ch2_OdtConfig = 0x00, + config->Ch2_TristateClk1 = 0x00, + config->Ch2_Mode2N = 0x00, + config->Ch2_OdtLevels = 0x00, + + config->Ch3_RankEnable = 0x03, + config->Ch3_DeviceWidth = 0x02, + config->Ch3_DramDensity = 0x02, + config->Ch3_Option = 0x03, + config->Ch3_OdtConfig = 0x00, + config->Ch3_TristateClk1 = 0x00, + config->Ch3_Mode2N = 0x00, + config->Ch3_OdtLevels = 0x00, + + config->RmtCheckRun = 0x00, + config->RmtMarginCheckScaleHighThreshold = 0x00; + config->MsgLevelMask = 0x00; + + memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling, + sizeof(ch0_bit_swizzling)); + memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling, + sizeof(ch1_bit_swizzling)); + memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling, + sizeof(ch2_bit_swizzling)); + memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling, + sizeof(ch3_bit_swizzling)); +} + +void mainboard_save_dimm_info(void) +{ + save_lpddr4_dimm_info(&lp4cfg, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e9b4d97a4799f58ffaf9f15554f45d6f7e12110 Gerrit-Change-Number: 62646 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Angel Pons has removed Joey Madafferi from this change. ( https://review.coreboot.org/c/coreboot/+/55494 ) Change subject: sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods ...................................................................... Removed cc Joey Madafferi. -- To view, visit https://review.coreboot.org/c/coreboot/+/55494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7 Gerrit-Change-Number: 55494 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Yu-Ping Wu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 19: -Code-Review (1 comment) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/e2bb3175_2a61e1e9 PS19, Line 23: /* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ : /* Some devices still need io ranges, reserve 16MB for compatibility */ : static struct mtk_pcie_mmio_res pcie_mmio_res_io = { : .cpu_addr = 0x20000000, : .pci_addr = 0x20000000, : .size = 16 * MiB, : .type = IORESOURCE_IO, : }; : : static struct mtk_pcie_mmio_res pcie_mmio_res_mem = { : .cpu_addr = 0x21000000, : .pci_addr = 0x21000000, : .size = 48 * MiB, : .type = IORESOURCE_MEM, : }; > These can be const, but CB:56791 needs to be updated to avoid compile-time errors about dropping "co […] I agree. -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:39:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
by Felix Held (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62578 ) Change subject: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: not sure why Jenkins failed; rebased it to see if that helps -- To view, visit https://review.coreboot.org/c/coreboot/+/62578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Gerrit-Change-Number: 62578 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 15:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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