coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by build bot (Jenkins) (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62645 ) Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... Patch Set 1: (4 comments) File src/mainboard/google/brya/variants/brya0/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143361): https://review.coreboot.org/c/coreboot/+/62645/comment/b5abf72a_70e719c6 PS1, Line 9: config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); line over 96 characters File src/mainboard/google/brya/variants/brya4es/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143361): https://review.coreboot.org/c/coreboot/+/62645/comment/59040ce6_b529c410 PS1, Line 9: config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); line over 96 characters File src/mainboard/google/brya/variants/kano/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143361): https://review.coreboot.org/c/coreboot/+/62645/comment/f5a6a9f1_9172bc8e PS1, Line 15: config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); line over 96 characters File src/mainboard/google/brya/variants/volmar/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143361): https://review.coreboot.org/c/coreboot/+/62645/comment/e50f72b8_ab568759 PS1, Line 9: config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:52:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 97: (7 comments) File src/mainboard/starlabs/labtop/variants/cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/58428/comment/dc3b9091_239df700 PS95, Line 2: # CPU > nit: missing a tab Done https://review.coreboot.org/c/coreboot/+/58428/comment/b0a938c0_701bdf3f PS95, Line 79: # Internal Webcam : register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" : # Internal Bluetooth : register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" > Internal USB ports shouldn't be assigned any overcurrent pins Done File src/mainboard/starlabs/labtop/variants/cml/gpio.c: https://review.coreboot.org/c/coreboot/+/58428/comment/a5613e15_73cb48f1 PS95, Line 19: PAD_CFG_GPI(GPP_H7, NONE, PLTRST), > You probably want to configure the pads for UART #2 here as well Done File src/mainboard/starlabs/labtop/variants/cml/hda_verb.c: https://review.coreboot.org/c/coreboot/+/58428/comment/0a0747f5_f8090dad PS95, Line 14: 0x10EC1200 > nit: drop value from comment, it's in the code already Done File src/mainboard/starlabs/labtop/variants/cml/romstage.c: https://review.coreboot.org/c/coreboot/+/58428/comment/6e5dea9f_c271d587 PS95, Line 11: u8 > Would `unsigned int` work? I'd like to drop the cast in the returned value. Done https://review.coreboot.org/c/coreboot/+/58428/comment/7fec130f_39e6fb10 PS95, Line 18: ID3 > nit: missing opening parenthesis Done https://review.coreboot.org/c/coreboot/+/58428/comment/2567afe8_8ee33422 PS95, Line 23: * 1 1 1 Samsung 4G single channel : * 1 1 0 Samsung 8G dual channel : * 1 0 1 Micron 4G single channel : * 1 0 0 Micron 8G dual channel : * 0 1 1 Hynix 4G single channel : * 0 1 0 Hynix 8G dual channel : * 0 0 1 Micron 16G dual channel : * 0 0 0 Hynix 16G dual channel > nit: Could you please invert the order of the rows? It makes more sense to start with `0 0 0` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 97 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/scout: Add i2c HID driver
by Rehan Ghori (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel. Rehan Ghori has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62591 ) Change subject: mb/google/hatch/scout: Add i2c HID driver ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Tim, thank you so much for a thorough review and a quick response. Is there anything I need to do to submit it? What else is left? Thanks again -- To view, visit https://review.coreboot.org/c/coreboot/+/62591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd Gerrit-Change-Number: 62591 Gerrit-PatchSet: 7 Gerrit-Owner: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joe Tessler <jrt(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:40:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62566/comment/a656d4db_77ae1eb8 PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at) > So you are referring to UFS, right? I am not familiar with UFS, I guess it is linear mapped into the BIOS region just like SPI? If yes, the address space needs to be reserved as well, right. I just not sure what happens after boot, doe the mapping remain or is it disabled later? Ah, yes, older platforms (APL, GLK) use eMMC, but newer platforms (ADL) use UFS. Good question, though: I don't know if the memory-mapping is disabled for eMMC/UFS later on. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:39:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/scout: Add i2c HID driver
by Tim Wawrzynczak (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Paul Menzel, Rehan Ghori. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62591 ) Change subject: mb/google/hatch/scout: Add i2c HID driver ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd Gerrit-Change-Number: 62591 Gerrit-PatchSet: 7 Gerrit-Owner: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joe Tessler <jrt(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... Patch Set 95: Code-Review+1 (8 comments) File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/58428/comment/37f853a2_e2afd964 PS95, Line 19: EC_STARLABS_FAN Already selected through `BOARD_STARLABS_LABTOP_SERIES`, looks like TGL also has this redundancy. Not sure if it's best to keep the select in the `_SERIES` Kconfig or specify it per-board. File src/mainboard/starlabs/labtop/variants/cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/58428/comment/cb9f0f21_a260e33c PS95, Line 2: # CPU nit: missing a tab https://review.coreboot.org/c/coreboot/+/58428/comment/1b66ec85_4cec5d2e PS95, Line 79: # Internal Webcam : register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" : # Internal Bluetooth : register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" Internal USB ports shouldn't be assigned any overcurrent pins File src/mainboard/starlabs/labtop/variants/cml/gpio.c: https://review.coreboot.org/c/coreboot/+/58428/comment/a1261d57_1e157ba3 PS95, Line 19: PAD_CFG_GPI(GPP_H7, NONE, PLTRST), You probably want to configure the pads for UART #2 here as well File src/mainboard/starlabs/labtop/variants/cml/hda_verb.c: https://review.coreboot.org/c/coreboot/+/58428/comment/f85cbddf_1efeef12 PS95, Line 14: 0x10EC1200 nit: drop value from comment, it's in the code already File src/mainboard/starlabs/labtop/variants/cml/romstage.c: https://review.coreboot.org/c/coreboot/+/58428/comment/1aed28b4_b10bc4c8 PS95, Line 11: u8 Would `unsigned int` work? I'd like to drop the cast in the returned value. https://review.coreboot.org/c/coreboot/+/58428/comment/600248bf_1e32de48 PS95, Line 18: ID3 nit: missing opening parenthesis https://review.coreboot.org/c/coreboot/+/58428/comment/4508448e_b8a05e15 PS95, Line 23: * 1 1 1 Samsung 4G single channel : * 1 1 0 Samsung 8G dual channel : * 1 0 1 Micron 4G single channel : * 1 0 0 Micron 8G dual channel : * 0 1 1 Hynix 4G single channel : * 0 1 0 Hynix 8G dual channel : * 0 0 1 Micron 16G dual channel : * 0 0 0 Hynix 16G dual channel nit: Could you please invert the order of the rows? It makes more sense to start with `0 0 0` -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 95 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:35:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Werner Zeh (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62566/comment/f92e91d0_baa4d2ea PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at) > I wasn't thinking about the loading speed, I was considering the flash resource declaration. […] So you are referring to UFS, right? I am not familiar with UFS, I guess it is linear mapped into the BIOS region just like SPI? If yes, the address space needs to be reserved as well, right. I just not sure what happens after boot, doe the mapping remain or is it disabled later? -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 14:29:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Hello Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#3). Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variables to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 34 files changed, 227 insertions(+), 226 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variable to snake case
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#2). Change subject: soc/intel/adl/chip.h: Convert all camel case variable to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variable to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 34 files changed, 227 insertions(+), 226 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variable names to snake ...
by Maulik V Vaghela (Code Review) 07 Mar '22

07 Mar '22

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62645 ) Change subject: soc/intel/adl/chip.h: Convert all camel case variable names to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variable names to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, many of variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 34 files changed, 227 insertions(+), 226 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/1 diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 2f79831..832f728 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -31,7 +31,7 @@ }" register "SaGv" = "SaGv_Enabled" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 @@ -43,7 +43,7 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -52,7 +52,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 08550d2..8729b3a 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -36,7 +36,7 @@ register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -45,7 +45,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 98dd3a5..096a713 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -20,7 +20,7 @@ register "tcc_offset" = "10" # TCC of 90 # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 @@ -41,7 +41,7 @@ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -50,12 +50,12 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoPci, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, @@ -68,13 +68,13 @@ register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # FIVR RFI Spread Spectrum 1.5% - register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + register "fivr_spread_spectrum" = "FIVR_SS_1_5" # This disables autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses. diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c index 9628b44..4d30b8e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -146,7 +146,7 @@ /* voltage unit is milliVolts and current is in milliAmps */ soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); - conf->PsysPmax = soc_config->psys_pmax; + conf->platform_pmax = soc_config->psys_pmax; soc_config->tdp_pl2_override = pl2; soc_config->tdp_psyspl2 = psyspl2; diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 6ac796a..306451b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -20,7 +20,7 @@ register "tcc_offset" = "10" # TCC of 90 # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 @@ -37,7 +37,7 @@ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -46,12 +46,12 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoPci, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, @@ -64,13 +64,13 @@ register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # FIVR RFI Spread Spectrum 1.5% - register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + register "fivr_spread_spectrum" = "FIVR_SS_1_5" # This disables autonomous GPIO power management, otherwise old cr50 FW # only supports short pulses and they can be missed by the PCH. diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 91c633a..8680ceb 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -15,7 +15,7 @@ register "s0ix_enable" = "1" # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # eMMC HS400 register "emmc_enable_hs400_mode" = "1" @@ -33,7 +33,7 @@ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -42,22 +42,22 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/brask/variant.c b/src/mainboard/google/brya/variants/brask/variant.c index 8e3578c..740b47b 100644 --- a/src/mainboard/google/brya/variants/brask/variant.c +++ b/src/mainboard/google/brya/variants/brask/variant.c @@ -6,5 +6,5 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S)); } diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 9f3e028..d080844 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -37,7 +37,7 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port @@ -46,7 +46,7 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" # Enable CNVi DDR RFIM - register "CnviDdrRfim" = "1" + register "cnvi_ddr_rfim" = "1" # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c index 8d4471b..906ff79 100644 --- a/src/mainboard/google/brya/variants/brya0/variant.c +++ b/src/mainboard/google/brya/variants/brya0/variant.c @@ -6,5 +6,5 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); } diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 13d028e..5c36ec0 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -37,7 +37,7 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port diff --git a/src/mainboard/google/brya/variants/brya4es/variant.c b/src/mainboard/google/brya/variants/brya4es/variant.c index 8d4471b..906ff79 100644 --- a/src/mainboard/google/brya/variants/brya4es/variant.c +++ b/src/mainboard/google/brya/variants/brya4es/variant.c @@ -6,5 +6,5 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); } diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index d184276..38506bf 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -30,7 +30,7 @@ register "tcss_ports[0]" = "TCSS_PORT_EMPTY" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -39,7 +39,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index 8b270de..b0bf99a 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -15,6 +15,6 @@ if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) { config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19; config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20; - config->TcssAuxOri = 0x10; + config->tcss_aux_ori = 0x10; } } diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 0d8b49b..63f5437 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -22,14 +22,14 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "143" - register "TcssAuxOri" = "1" + register "platform_pmax" = "143" + register "tcss_aux_ori" = "1" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram diff --git a/src/mainboard/google/brya/variants/gimble/variant.c b/src/mainboard/google/brya/variants/gimble/variant.c index 96ccf88..48a3f21 100644 --- a/src/mainboard/google/brya/variants/gimble/variant.c +++ b/src/mainboard/google/brya/variants/gimble/variant.c @@ -12,6 +12,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1)); } diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 1ab9a7e..0922cae 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -22,14 +22,14 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "143" - register "TcssAuxOri" = "1" + register "platform_pmax" = "143" + register "tcss_aux_ori" = "1" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram diff --git a/src/mainboard/google/brya/variants/gimble4es/variant.c b/src/mainboard/google/brya/variants/gimble4es/variant.c index 96ccf88..48a3f21 100644 --- a/src/mainboard/google/brya/variants/gimble4es/variant.c +++ b/src/mainboard/google/brya/variants/gimble4es/variant.c @@ -12,6 +12,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1)); } diff --git a/src/mainboard/google/brya/variants/kano/variant.c b/src/mainboard/google/brya/variants/kano/variant.c index 0db43aa..e283ed3 100644 --- a/src/mainboard/google/brya/variants/kano/variant.c +++ b/src/mainboard/google/brya/variants/kano/variant.c @@ -12,5 +12,5 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); } diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 36fee91..0cd3d47 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -24,13 +24,14 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "MaxDramSpeed" = "3733" + register "max_dram_speed" = "3733" + # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 77218b0..ccf54ca 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -24,13 +24,14 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "MaxDramSpeed" = "3733" + register "max_dram_speed" = "3733" + # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 62a24ed..3ffbbc1 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -32,14 +32,14 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_audio_offload" = "true" # FIVR RFI Spread Spectrum 6% - register "FivrSpreadSpectrum" = "FIVR_SS_6" + register "fivr_spread_spectrum" = "FIVR_SS_6" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 5cb105d..5da5049 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -32,14 +32,14 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_audio_offload" = "true" # FIVR RFI Spread Spectrum 6% - register "FivrSpreadSpectrum" = "FIVR_SS_6" + register "fivr_spread_spectrum" = "FIVR_SS_6" # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index ac83e58..507ee34 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,11 +41,11 @@ end chip soc/intel/alderlake # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, @@ -59,7 +59,7 @@ .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" @@ -115,7 +115,7 @@ }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 11d572f..a720c2b 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -40,11 +40,12 @@ end chip soc/intel/alderlake # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, @@ -58,7 +59,8 @@ .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" @@ -107,7 +109,7 @@ }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index f80f5d6..5253ff9 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -49,11 +49,11 @@ .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" - register "PsysPmax" = "145" + register "platform_pmax" = "145" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 @@ -94,7 +94,7 @@ }, }" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 1562482..5d12aaa 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -53,7 +53,7 @@ register "SaGv" = "SaGv_Enabled" # I2C Port Config - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index f54753b..45a43a7 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -23,7 +23,7 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "TcssAuxOri" = "1" + register "tcss_aux_ori" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c index fef03f2..09b2a28 100644 --- a/src/mainboard/google/brya/variants/volmar/variant.c +++ b/src/mainboard/google/brya/variants/volmar/variant.c @@ -6,5 +6,5 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); } diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 9bd99b1..d9319a6 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -11,7 +11,7 @@ # FSP configuration # Enable CNVi BT - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # Sagv Configuration register "SaGv" = "SaGv_Enabled" @@ -95,16 +95,16 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, [2] = 1, @@ -112,19 +112,19 @@ }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "0" + register "tcss_aux_ori" = "0" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -133,40 +133,40 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_audio_offload" = "true" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index c637ec3..c0d86fa 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -39,7 +39,7 @@ register "SaGv" = "SaGv_Enabled" # Enable CNVi Bluetooth - register "CnviBtCore" = "true" + register "cnvi_bt_core" = "true" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -80,7 +80,7 @@ }" # Hybrid storage mode - register "HybridStorageMode" = "1" + register "hybrid_storage_mode" = "1" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ @@ -90,18 +90,18 @@ }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "0" + register "tcss_aux_ori" = "0" register "s0ix_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, @@ -110,38 +110,38 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index f7da2d1..a5634c1 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -11,7 +11,7 @@ # FSP configuration # Enable CNVi BT - register "CnviBtCore" = "true" + register ""cnvi_bt_core"" = "true" # Sagv Configuration register "SaGv" = "SaGv_Enabled" @@ -54,16 +54,16 @@ .flags = PCIE_RP_CLK_REQ_DETECT, }" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, [2] = 1, @@ -71,19 +71,19 @@ }" # Enable EDP in PortA - register "DdiPortAConfig" = "1" + register "ddi_portA_config" = "1" # Enable HDMI in Port B register "ddi_ports_config" = "{ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" # TCSS USB3 - register "TcssAuxOri" = "4" + register "tcss_aux_ori" = "4" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" register "s0ix_enable" = "1" - register "SerialIoI2cMode" = "{ + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, @@ -92,40 +92,40 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "SerialIoGSpiMode" = "{ + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" - register "SerialIoGSpiCsMode" = "{ + register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoGSpiCsState" = "{ + register "serial_io_gspi_cs_state" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" - register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" - register "PchHdaIDispCodecEnable" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" - register "CnviBtAudioOffload" = "true" + register "cnvi_bt_core" = "true" # Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index aad45df..73ef206 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -195,9 +195,9 @@ /* Enable S0iX support */ int s0ix_enable; /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - uint8_t TcssD3HotDisable; + uint8_t tcss_d3_hot_disable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdDisable; + uint8_t tcss_d3_cold_disable; /* Enable DPTF support */ int dptf_enable; @@ -243,31 +243,31 @@ struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; /* SATA related */ - uint8_t SataEnable; - uint8_t SataMode; - uint8_t SataSalpSupport; - uint8_t SataPortsEnable[8]; - uint8_t SataPortsDevSlp[8]; + uint8_t sata_mode; + uint8_t sata_salp_support; + uint8_t sata_ports_enable[8]; + uint8_t sata_ports_dev_slp[8]; /* * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. * Default 0. Setting this to 1 disables the SATA Power Optimizer. */ - uint8_t SataPwrOptimizeDisable; + uint8_t sata_pwr_optimize_disable; /* * SATA Port Enable Dito Config. * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). */ - uint8_t SataPortsEnableDitoConfig[8]; + uint8_t sata_ports_enable_dito_config[8]; /* SataPortsDmVal is the DITO multiplier. Default is 15. */ - uint8_t SataPortsDmVal[8]; + uint8_t sata_ports_dm_val[8]; + /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ - uint16_t SataPortsDitoVal[8]; + uint16_t sata_ports_dito_val[8]; /* Audio related */ - uint8_t PchHdaDspEnable; + uint8_t pch_hda_dsp_enable; /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ enum { @@ -275,15 +275,15 @@ HDA_TMODE_4T = 2, HDA_TMODE_8T = 3, HDA_TMODE_16T = 4, - } PchHdaIDispLinkTmode; + } pch_hda_idisp_link_tmode; /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ enum { HDA_LINKFREQ_48MHZ = 3, HDA_LINKFREQ_96MHZ = 4, - } PchHdaIDispLinkFrequency; + } pch_hda_idisp_link_frequency; - bool PchHdaIDispCodecEnable; + bool pch_hda_idisp_codec_enable; struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; @@ -311,8 +311,8 @@ IGD_SM_52MB = 0xFC, IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, - } IgdDvmt50PreAlloc; - uint8_t SkipExtGfxScan; + } igd_dvmt50_pre_alloc; + uint8_t skip_ext_gfx_scan; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; @@ -328,21 +328,21 @@ * PchSerialIoLegacyUart, * PchSerialIoSkipInit */ - uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; - uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX]; /* * GSPIn Default Chip Select Mode: * 0:Hardware Mode, * 1:Software Mode */ - uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; /* * GSPIn Default Chip Select State: * 0: Low, * 1: High */ - uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; /* Debug interface selection */ enum { @@ -357,10 +357,10 @@ uint8_t pch_isclk; /* CNVi BT Core Enable/Disable */ - bool CnviBtCore; + bool cnvi_bt_core; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - bool CnviBtAudioOffload; + bool cnvi_bt_audio_offload; /* * These GPIOs will be programmed by the IOM to handle biasing of the @@ -379,10 +379,7 @@ * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines * on the motherboard. */ - uint16_t TcssAuxOri; - - /* Connect Topology Command timeout value */ - uint16_t ITbtConnectTopologyTimeoutInMs; + uint16_t tcss_aux_ori; /* * Override GPIO PM configuration: @@ -408,8 +405,8 @@ * Port config * 0:Disabled, 1:eDP, 2:MIPI DSI */ - uint8_t DdiPortAConfig; - uint8_t DdiPortBConfig; + uint8_t ddi_portA_config; + uint8_t ddi_portB_config; /* Enable(1)/Disable(0) HPD/DDC */ uint8_t ddi_ports_config[DDI_PORT_COUNT]; @@ -417,7 +414,7 @@ /* Hybrid storage mode enable (1) / disable (0) * This mode makes FSP detect Optane and NVME and set PCIe lane mode * accordingly */ - uint8_t HybridStorageMode; + uint8_t hybrid_storage_mode; #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* eMMC HS400 mode */ @@ -441,19 +438,19 @@ * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. * Default 0. Setting this to 1 disables the DMI Power Optimizer. */ - uint8_t DmiPwrOptimizeDisable; + uint8_t dmi_power_optimize_disable; /* * Enable(1)/Disable(0) CPU Replacement check. * Default 0. Setting this to 1 to check CPU replacement. */ - uint8_t CpuReplacementCheck; + uint8_t cpu_replacement_check; /* ISA Serial Base selection. */ enum { ISA_SERIAL_BASE_ADDR_3F8, ISA_SERIAL_BASE_ADDR_2F8, - } IsaSerialUartBase; + } isa_serial_uart_base; /* structure containing various settings for PCH FIVRs */ struct { @@ -480,7 +477,7 @@ */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - uint16_t MaxDramSpeed; + uint16_t max_dram_speed; enum { SLP_S3_ASSERTION_DEFAULT, @@ -532,7 +529,7 @@ } pch_reset_power_cycle_duration; /* Platform Power Pmax */ - uint16_t PsysPmax; + uint16_t platform_pmax; /* * FivrRfiFrequency * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. @@ -541,7 +538,7 @@ * 0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock * 0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock */ - uint32_t FivrRfiFrequency; + uint32_t fivr_rfi_frequency; /* * FivrSpreadSpectrum * Set the Spread Spectrum Range. @@ -549,21 +546,21 @@ * Each Range is translated to an encoded value for FIVR register. * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. */ - uint8_t FivrSpreadSpectrum; + uint8_t fivr_spread_spectrum; /* Enable or Disable Acoustic Noise Mitigation feature */ - uint8_t AcousticNoiseMitigation; + uint8_t acoustic_noise_mitigation; /* Disable Fast Slew Rate for Deep Package C States for VR domains */ - uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS]; + uint8_t fast_pkg_c_ramp_disable[NUM_VR_DOMAINS]; /* * Slew Rate configuration for Deep Package C States for VR domains * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ - uint8_t SlowSlewRate[NUM_VR_DOMAINS]; + uint8_t slow_slew_rate[NUM_VR_DOMAINS]; /* CNVi DDR RFIM Enable/Disable * Default 0. Setting this to 1 enable CNVi DDR RFIM. */ - bool CnviDdrRfim; + bool cnvi_ddr_rfim; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index dac3693..138efd2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -337,16 +337,16 @@ const struct soc_intel_alderlake_config *config) { for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) - s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i]; for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { - s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; - s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; - s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i]; + s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; + s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; } for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) - s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; + s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; } static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, @@ -393,7 +393,7 @@ DEV_PTR(tcss_usb3_port4), }; - s_cfg->TcssAuxOri = config->TcssAuxOri; + s_cfg->TcssAuxOri = config->tcss_aux_ori; /* Explicitly clear this field to avoid using defaults */ memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); @@ -406,8 +406,8 @@ s_cfg->ITbtConnectTopologyTimeoutInMs = 0; /* D3Hot and D3Cold for TCSS */ - s_cfg->D3HotEnable = !config->TcssD3HotDisable; - s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; + s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; + s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -497,11 +497,11 @@ /* SATA */ s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); if (s_cfg->SataEnable) { - s_cfg->SataMode = config->SataMode; - s_cfg->SataSalpSupport = config->SataSalpSupport; - memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, + s_cfg->SataMode = config->sata_mode; + s_cfg->SataSalpSupport = config->sata_salp_support; + memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, sizeof(s_cfg->SataPortsEnable)); - memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, + memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, sizeof(s_cfg->SataPortsDevSlp)); } @@ -511,17 +511,17 @@ * Boards not needing the optimizers explicitly disables them by setting * these disable variables to 1 in devicetree overrides. */ - s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); /* * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. * SataPortsDmVal is the DITO multiplier. Default is 15. * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. * The default values can be changed from devicetree. */ - for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { - if (config->SataPortsEnableDitoConfig[i]) { - s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; - s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; + for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { + if (config->sata_ports_enable_dito_config[i]) { + s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; + s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; } } } @@ -548,8 +548,8 @@ { /* CNVi */ s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); - s_cfg->CnviBtCore = config->CnviBtCore; - s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; + s_cfg->CnviBtCore = config->cnvi_bt_core; + s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; /* Assert if CNVi BT is enabled without CNVi being enabled. */ assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ @@ -611,7 +611,7 @@ s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; #endif /* Enable Hybrid storage auto detection */ - s_cfg->HybridStorageMode = config->HybridStorageMode; + s_cfg->HybridStorageMode = config->hybrid_storage_mode; } static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, @@ -663,7 +663,7 @@ * Boards not needing the optimizers explicitly disables them by setting * these disable variables to 1 in devicetree overrides. */ - s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); + s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable); s_cfg->PmSupport = 1; s_cfg->Hwp = 1; s_cfg->Cx = 1; @@ -712,10 +712,10 @@ power_cycle_duration); /* Set PsysPmax if it is available from DT */ - if (config->PsysPmax) { - printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax); + if (config->platform_pmax) { + printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax); /* PsysPmax is in unit of 1/8 Watt */ - s_cfg->PsysPmax = config->PsysPmax * 8; + s_cfg->PsysPmax = config->platform_pmax * 8; } } @@ -776,19 +776,19 @@ const struct soc_intel_alderlake_config *config) { /* transform from Hz to 100 KHz */ - s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz); - s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; + s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz); + s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum; } static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { - s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation; if (s_cfg->AcousticNoiseMitigation) { for (int i = 0; i < NUM_VR_DOMAINS; i++) { - s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; - s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i]; + s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i]; + s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i]; } } } diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index e0f5eb7..51db5e2 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -114,8 +114,8 @@ /* IGD is enabled, set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; /* DP port config */ - m_cfg->DdiPortAConfig = config->DdiPortAConfig; - m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAConfig = config->ddi_portA_config; + m_cfg->DdiPortBConfig = config->ddi_portB_config; for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & DDI_ENABLE_DDC); @@ -139,8 +139,8 @@ { m_cfg->SaGv = config->SaGv; m_cfg->RMT = config->RMT; - if (config->MaxDramSpeed) - m_cfg->DdrFreqLimit = config->MaxDramSpeed; + if (config->max_dram_speed) + m_cfg->DdrFreqLimit = config->max_dram_speed; } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, @@ -202,13 +202,13 @@ m_cfg->LockPTMregs = 0; /* Skip CPU replacement check */ - m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; /* Skip GPIO configuration from FSP */ m_cfg->GpioOverride = 0x1; /* CNVi DDR RFI Mitigation */ - m_cfg->CnviDdrRfim = config->CnviDdrRfim; + m_cfg->CnviDdrRfim = config->cnvi_ddr_rfim; } static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, @@ -216,10 +216,10 @@ { /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); - m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; + m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; + m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; + m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; + m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to * configure GPIO pads for audio. Mainboard is expected to perform all GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022