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Change subject: images: Add coreboot_hare.svg
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Can the logo for edk2 sit here?
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Change subject: device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File src/arch/arm/include/armv4/arch/mmio.h:
https://review.coreboot.org/c/coreboot/+/62561/comment/263a6363_ce123d05
PS6, Line 28: uint64_t read64(const void *addr);
I love this approach!
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Change subject: soc/mediatek/mt8195: Add driver to configure PCIe
......................................................................
Patch Set 19:
(1 comment)
File src/soc/mediatek/mt8195/pcie.c:
https://review.coreboot.org/c/coreboot/+/56792/comment/e07720fb_9a65edd4
PS10, Line 70: 0x112f0000
> Angel, are you okay with the latest PS17?
Yes, I'm OK with the macro.
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Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons.
Hello build bot (Jenkins), Andy Pont, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58428
to look at the new patch set (#94).
Change subject: mb/starlabs/labtop: Add LabTop Mk IV
......................................................................
mb/starlabs/labtop: Add LabTop Mk IV
Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21
No known issues.
https://starlabs.systems/pages/labtop-mk-iv-specification
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c
---
M Documentation/mainboard/index.md
A Documentation/mainboard/starlabs/labtop_cml.md
M src/mainboard/starlabs/labtop/Kconfig
M src/mainboard/starlabs/labtop/Kconfig.name
M src/mainboard/starlabs/labtop/Makefile.inc
M src/mainboard/starlabs/labtop/dsdt.asl
A src/mainboard/starlabs/labtop/spd/Makefile.inc
A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
A src/mainboard/starlabs/labtop/variants/cml/board.fmd
A src/mainboard/starlabs/labtop/variants/cml/data.vbt
A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
A src/mainboard/starlabs/labtop/variants/cml/devtree.c
A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/cml/gpio.c
A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c
A src/mainboard/starlabs/labtop/variants/cml/romstage.c
19 files changed, 1,305 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/58428/94
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/80bf18d9_13b310d8
PS2, Line 15: Now, in this scenario, the SPI
: flash linear address range is not registered as a resource (since the
: common SPI driver in src/soc/intel/common/block/spi is shared across
: multiple SPI controllers and therefore cannot distinguish where the
: flash is actually located at)
> Having boot firmware on eMMC wouldn't be such an issue even in uncached case I guess since eMMC prov […]
I wasn't thinking about the loading speed, I was considering the flash resource declaration. Only *SPI* flash would be attached to the fast SPI controller, the fast SPI controller could even be disabled on systems that boot off eMMC. That's why I don't want to declare the flash resource (i.e. memory-mapped SPI or eMMC) from the fast SPI controller device.
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Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/eaf9b474_ca80bc67
PS2, Line 15: Now, in this scenario, the SPI
: flash linear address range is not registered as a resource (since the
: common SPI driver in src/soc/intel/common/block/spi is shared across
: multiple SPI controllers and therefore cannot distinguish where the
: flash is actually located at)
> Actually, I'm not sure what would happen on systems without SPI flash. […]
Having boot firmware on eMMC wouldn't be such an issue even in uncached case I guess since eMMC provides a way more faster interface.
The case I was facing hurts so bad because I can only offer a 20 MHz single SPI channel.
Maybe the LPC/eSPI driver could be a good place for this resource. There is a common LPC driver for it and there is usually just one eSPI controller around. Nevertheless it is not 100% accurate because the flash is physically attached to the fast-SPI controller. Maybe we really should add jet another common driver just for the fast-SPI controller.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62289 )
Change subject: payloads/iPXE: Update stable version from 2019.3 to to 2022.1
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62289/comment/b481f2cd_b919fc59
PS1, Line 20: 2021-09-23_b0d87f753c (builds the iPXE master only).
> Build-testing iPXE automatically would be nice.
Christian? Can you mark the discussion as resolved if your concern has been addressed?
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60877
to look at the new patch set (#16).
Change subject: sb/intel/common/firmware: Hook up adding 10GbE LAN firmware
......................................................................
sb/intel/common/firmware: Hook up adding 10GbE LAN firmware
Add ability to use ifdtool to add LAN firmware to image using Kconfig
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3
---
M src/southbridge/intel/common/firmware/Kconfig
M src/southbridge/intel/common/firmware/Makefile.inc
2 files changed, 51 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/60877/16
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