coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/denverton_ns/chip.c: add soc_acpi_name function
by Jeff Daly (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Jeff Daly has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60991 ) Change subject: soc/intel/denverton_ns/chip.c: add soc_acpi_name function ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: > Patchset 11 was ok but in 12 unrelated whitespace changes are back :( yes, i realized after the fact that i had done merge with a local branch that contained and older version of the patch train. :( PS12: will be reverting this and doing a proper rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/60991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce Gerrit-Change-Number: 60991 Gerrit-PatchSet: 12 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 12:21:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#13). Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... libpayload/pci: Add PCIe interfaces for MediaTek platform Add PCIe configuration interfaces for MediaTek platform. The register base address of PCIe hardware might be different when it's a non-x86 platform, add 'pci_update_hw_base()' interface for users to update its base address to access PCIe hardware correctly. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c M payloads/libpayload/include/pci.h 4 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Furquan Shaikh. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#12). Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... libpayload/pci: Split PCI interfaces as common and chip related Move the common APIs to pci_common.c and others to the chip related file. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc C payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 102 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62566/comment/945fa5d9_e7ed73a3 PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at) > Yes, like Angel mentioned already the fast_spi driver is not bound to a PCI device. […] Actually, I'm not sure what would happen on systems without SPI flash. I think it's possible to have boot firmware in eMMC, and it would still be memory-mapped. Hmmm, if this can happen, we should declare the resource from the LPC/eSPI device instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 12:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Change all USB ports to OC0
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62423 ) Change subject: mb/starlabs/labtop: Change all USB ports to OC0 ...................................................................... Abandoned Incorrect -- To view, visit https://review.coreboot.org/c/coreboot/+/62423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d0ed3b3cbe331e3e9455b7b04e938616458e739 Gerrit-Change-Number: 62423 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/tgl: add device UART #3 to chipset devicetree
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62624 ) Change subject: soc/intel/tgl: add device UART #3 to chipset devicetree ...................................................................... Patch Set 2: Code-Review-1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62624/comment/dceaae5f_9ad5eb8d PS2, Line 9: Reference: Intel doc# 631119-007 The only reference to UART controller #3 I could find in this document is in `Table 6. PCH-UP3/UP4 Device and Revision ID Table`. The rest of the document says/implies there are only 3 UART controllers (0, 1, 2). Do you have other sources that confirm the existence of UART controller #3? Are there any pads for this UART #3? Patchset: PS2: I'm not convinced that this device actually exists. My -1 is because uart.c needs to be updated accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/62624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3abccf65d59278b38835cdfda9e54991d6edaacf Gerrit-Change-Number: 62624 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 11:52:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: drop orphaned VR domains enum
by Angel Pons (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62622 ) Change subject: soc/intel/tgl: drop orphaned VR domains enum ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Gerrit-Change-Number: 62622 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 11:51:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Werner Zeh (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62566/comment/f9cfcce1_c017cda6 PS2, Line 10: done by FSP > @Werner, few clarification questions: […] Yes Subrata, sorry for being unprecise. On Eklhart Lake (where I have discovered this issue) the MP init is executed in hybrid mode where FSP do the init and coreboot provides the callbacks. https://review.coreboot.org/c/coreboot/+/62566/comment/1450a901_bf5c963f PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at) > > I don't understand this. […] Yes, like Angel mentioned already the fast_spi driver is not bound to a PCI device. I have had a quick look at the generic SPI driver and the bus_ops are only used for ACPI use cases. Doing this properly needs to refactor the SPI driver. But again, the painful thing here is the broad usage of the common driver. We would need a dedicated SPI bus driver just for the bus where the flash is attached to. Or we can add a callback into soc code to ask it _this_ SPI controller owns the flash and add the needed resource for this controller in the common code. I though a bit about placing a resource in the system agent but it looks weird as the SPI flash is not part of it. https://review.coreboot.org/c/coreboot/+/62566/comment/adabdce2_01addbca PS2, Line 19: uncached flash : range > I thought flashed mapped range is always cached and DRAM resource allocation is not clearing that. […] The thing here is like described: Once coreboot MTRR setup is executed, the ranges are computed based on the resources already registered. If there is no resource around covering the flash region, it will not be taken into account and hence the MTRR will not be set up for it (according to the debug logs I have enabled for MTRR debugging). https://review.coreboot.org/c/coreboot/+/62566/comment/f7f35f80_60388570 PS2, Line 20: The result of this chain is : that loading the payload from flash takes much longer now (on mc_ehl1 it : takes ~12 seconds for 4.5 MB). > Interesting. […] There is a chance that this is indeed platform related. So if somebody can do some test on affected platforms that would be super helpful. For instance the same mainboard (meaning same SPI bus routing and speed settings) with a Broadwell-DE loads the same payload in 1.6 seconds. My first though was: maybe due to the larger cache (6 MB Broadwell-DE vs. 1.5 Elkhart Lake). File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/62566/comment/1e1509e9_78d3570b PS2, Line 164: MP_SERVICES_PPI > Adding Intel ADL team to check if they are also seeing this regression. […] At least what I have heared from Sheng Alder Lake is affected, too. https://review.coreboot.org/c/coreboot/+/62566/comment/abfc18fe_2e6d2fac PS2, Line 165: mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, > The only platform that does this is amd/pi/00730F01. […] It was just handy to re-use the macros defined for this purpose there. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 11:46:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Furquan Shaikh. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56789/comment/f87d6a2b_a39a7c4f PS2, Line 7: Split PCI interfaces as common and chip related > I haven't looked at the entire chain in detail yet, but I had provided some feedback on CB:53903 w. […] Thanks for the suggestion, I add 'pci_map_bus()' for users to get the base address of config space in CL:56794. Normally for embedded platform, the base address of PCIe hardware might be different, so I also provide a 'pci_update_hw_base()' function for users(e.g. depthcharge) to set its hardware base address, is that ok? -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 11 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 11:22:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Rex-BC Chen (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 12: (1 comment) File payloads/libpayload/include/pci.h: https://review.coreboot.org/c/coreboot/+/56794/comment/77b2832f_4c877a60 PS3, Line 116: void pci_update_hw_base(uintptr_t base); > Added introduction to commit message, thanks. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 10:59:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022