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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 11:
(2 comments)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/61020/comment/5b1fe922_7020096c
PS11, Line 9: #include <soc/soc_chip.h>
Since every SoC won't have soc_chip.h, compilation issue is seen. Need to remove this line.
https://review.coreboot.org/c/coreboot/+/61020/comment/38e6104e_68337c0a
PS11, Line 152: static void wifi_dsm_ddrrfim_func3_cb(void *ptr)
You can create a weak function here (example: get_wifi_sar_limits), which returns default value (0) and SoC can override that function if required.
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Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init
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Patch Set 7: Code-Review+2
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Change subject: cpu/x86/lapic: Unify some parameter
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Patch Set 2: Code-Review+2
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Change subject: cpu/x86/lapic: Support switching to X2APIC mode
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Patch Set 16: Code-Review+2
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
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Patch Set 6: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Mohan Viswanathan, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61462
to look at the new patch set (#8).
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is requred. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=Test on guybrush that PSP receives message.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
3 files changed, 59 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/8
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 7:
(3 comments)
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/4a6ce2b7_b81a7e7d
PS6, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(3)
> This should be BIT(12). PSP sets bit 12 to indicate fusing is required.
Done
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/4b17120e_3d3bd65d
PS5, Line 124: static u32 soc_read_c2p38(void)
> commented on https://review.coreboot.org/c/coreboot/+/60968/11/src/soc/amd/common/block/…. […]
Done
https://review.coreboot.org/c/coreboot/+/61462/comment/e1149d4d_884876f8
PS5, Line 128: return 0;
> not sure if this will do the right thing in the error case; the other implementation linked above mi […]
Done
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