coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by build bot (Jenkins) (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 7: (2 comments) File src/soc/amd/common/block/psp/psp_gen2.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139996): https://review.coreboot.org/c/coreboot/+/61462/comment/b8d2d113_a826632a PS7, Line 128: if (!psp_mmio){ suspect code indent for conditional statements (8, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139996): https://review.coreboot.org/c/coreboot/+/61462/comment/c648f4c5_9f56c44a PS7, Line 128: if (!psp_mmio){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 7 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Feb 2022 12:37:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Jason Glenesk (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Mohan Viswanathan, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61462 to look at the new patch set (#7). Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... soc/amd/common/block/psp: add PSP command Add PSP command to send SPL fuse command if PSP indicates SPL fusing is requred. Also add Kconfig option to enable sending message. BUG=b:180701885 TEST=Test on guybrush that PSP receives message. Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 3 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 7 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61588 ) Change subject: soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function ...................................................................... soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config` override function from Alder Lake SoC as the required config (SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock configuration using SMM is not enabled. Note: The current assumption is that the responsibility of locking the sensitive GPIOs (from getting reprogrammed by OS or other SW) remains with the mainboard. BUG=b:208827718 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/gpio.c 1 file changed, 0 insertions(+), 57 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, but someone else must approve Maulik V Vaghela: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index bf067b2..dc5847d 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -265,60 +265,3 @@ *num = ARRAY_SIZE(routes); return routes; }; - -/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */ -static const struct gpio_lock_config gpios_to_lock[] = { - { GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */ - { GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */ - { GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */ - { GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */ - { GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */ - { GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */ - { GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */ - { GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */ - { GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */ - { GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */ - { GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */ - { GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */ - { GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */ - { GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */ - { GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */ - { GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */ - { GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */ - { GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */ - { GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */ - { GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */ - { GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */ - { GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */ - { GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */ - { GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */ - { GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */ - { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ - { GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */ - { GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */ - - { GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */ - { GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */ - { GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */ - { GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */ - { GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */ - { GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */ - { GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */ - { GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */ - { GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */ - { GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */ - { GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */ - { GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */ - { GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */ - { GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */ - { GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */ - { GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */ - - { GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */ -}; - -const struct gpio_lock_config *soc_gpio_lock_config(size_t *num) -{ - *num = ARRAY_SIZE(gpios_to_lock); - return gpios_to_lock; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/61588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8 Gerrit-Change-Number: 61588 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Remove GPIO PAD lock config override from mainboard
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61587 ) Change subject: soc/intel/common: Remove GPIO PAD lock config override from mainboard ...................................................................... soc/intel/common: Remove GPIO PAD lock config override from mainboard This patch removes mainboard capability to override GPIO PAD lock configuration using `mb_gpio_lock_config` override function as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 0 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index b37dd12..d5cc8fe 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -260,12 +260,6 @@ const struct gpio_lock_config *soc_gpio_lock_config(size_t *num); /* - * Returns an array of gpio_lock_config entries that the mainboard - * deems security risks that should be locked down. - */ -const struct gpio_lock_config *mb_gpio_lock_config(size_t *num); - -/* * Returns the pmc_gpe to gpio_gpe mapping table * */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 32de2f6..0cde289 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -317,32 +317,17 @@ return NULL; } -__weak const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) -{ - *num = 0; - return NULL; -} - static void soc_lock_gpios(void) { const struct gpio_lock_config *soc_gpios; - const struct gpio_lock_config *mb_gpios; size_t soc_gpio_num; - size_t mb_gpio_num; /* get list of gpios from SoC */ soc_gpios = soc_gpio_lock_config(&soc_gpio_num); - /* get list of gpios from mainboard */ - mb_gpios = mb_gpio_lock_config(&mb_gpio_num); - /* Lock any soc requested gpios */ if (soc_gpio_num) gpio_lock_pads(soc_gpios, soc_gpio_num); - - /* Lock any mainboard requested gpios */ - if (mb_gpio_num) - gpio_lock_pads(mb_gpios, mb_gpio_num); } static void finalize(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Gerrit-Change-Number: 61587 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61520 to look at the new patch set (#6). Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... soc/intel/common/cse: Add function to perform CSE lock configuration This patch implements `cse_lock_config()` to perform the required CSE lock configuration as per ME BWG (doc: 627331). BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61520/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... soc/intel/{adl, common}: Add routines into CSE IA-common code This patch adds routines to keep CSE and other HECI devices into the lower power device state (AKA D0I3). - cse_set_to_d0i3 => Set CSE device state to D0I3 - heci_set_to_d0i3 => Function sets D0I3 for all HECI devices Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI device count info from SoC layer to common CSE block. As per PCH EDS, the HECI device count for various SoCs are: ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4) APL => 1 (CSE) SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3) BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/skylake/Kconfig M src/soc/intel/xeon_sp/Kconfig 7 files changed, 50 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 880e1e0..b31395d 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -80,23 +80,6 @@ sa_lock_pam(); } -static void heci_finalize(void) -{ - unsigned int cse_dev[] = { - PCH_DEVFN_CSE, - PCH_DEVFN_CSE_2, - PCH_DEVFN_CSE_3, - PCH_DEVFN_CSE_4 - }; - - for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { - if (!is_cse_devfn_visible(cse_dev[i])) - continue; - - set_cse_device_state(cse_dev[i], DEV_IDLE); - } -} - static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -105,7 +88,7 @@ apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); - heci_finalize(); + heci_set_to_d0i3(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cd0abf7..38e7491 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,6 +120,10 @@ config DISABLE_HECI1_AT_PRE_BOOT default y +config MAX_HECI_DEVICES + int + default 1 + config MAX_CPUS int default 4 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1a112bd6..164159c 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -1,10 +1,3 @@ -config SOC_INTEL_COMMON_BLOCK_CSE - bool - default n - help - Driver for communication with Converged Security Engine (CSE) - over Host Embedded Controller Interface (HECI) - config DISABLE_HECI1_AT_PRE_BOOT bool "Disable HECI1 at the end of boot" depends on SOC_INTEL_COMMON_BLOCK_CSE @@ -14,6 +7,17 @@ Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload. +config MAX_HECI_DEVICES + int + default 6 + +config SOC_INTEL_COMMON_BLOCK_CSE + bool + default n + help + Driver for communication with Converged Security Engine (CSE) + over Host Embedded Controller Interface (HECI) + config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32f6d4f..6dfe329 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -988,6 +988,26 @@ return true; } +void cse_set_to_d0i3(void) +{ + if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) + return; + + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); +} + +/* Function to set D0I3 for all HECI devices */ +void heci_set_to_d0i3(void) +{ + for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i)); + if (!is_cse_devfn_visible(dev)) + continue; + + set_cse_device_state(dev, DEV_IDLE); + } +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 15b7313..c2efab1 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -489,6 +489,12 @@ /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); +/* Set CSE device state to D0I3 */ +void cse_set_to_d0i3(void); + +/* Function sets D0I3 for all HECI devices */ +void heci_set_to_d0i3(void); + /* * SoC override API to make heci1 disable using PCR. * diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 31e733c..5addfb2 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -87,6 +87,10 @@ select UDELAY_TSC select UDK_2015_BINDING +config MAX_HECI_DEVICES + int + default 5 + config MAX_CPUS int default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 0f025ac..32c2380 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -75,6 +75,10 @@ int default 2 +config MAX_HECI_DEVICES + int + default 5 + # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 04 Feb '22

04 Feb '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61550 ) Change subject: payloads/tianocore: Rework Makefile ...................................................................... Abandoned Merged into 61620 -- To view, visit https://review.coreboot.org/c/coreboot/+/61550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52e0afa7744f4a902274c41aed59ca23fd9f5fc Gerrit-Change-Number: 61550 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61620 to look at the new patch set (#9). Change subject: payloads/tianocore: Rework Makefile ...................................................................... payloads/tianocore: Rework Makefile Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This includes 3 new options: * TIANOCORE_BOOT_MANAGER_ESCAPE * TIANOCORE_HAVE_EFI_SHELL * TIANOCORE_FOLLOW_BGRT_SPEC This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61620/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/61620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Gerrit-Change-Number: 61620 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Set project_dir based on repo and branch
by Sean Rhodes (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61620 to look at the new patch set (#8). Change subject: payloads/tianocore: Set project_dir based on repo and branch ...................................................................... payloads/tianocore: Set project_dir based on repo and branch Set the project directory based on the git repository name and branch. i.e. mrchromebox+uefipayload_202107 This allows switching between repositories without deleting anything. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61620/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Gerrit-Change-Number: 61620 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/Makefile.inc: Build smi_trigger on !HAVE_SMI_HANDLER
by Angel Pons (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59913 ) Change subject: cpu/x86/Makefile.inc: Build smi_trigger on !HAVE_SMI_HANDLER ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie57819b3d169311371a1caca83c9b0c796b46048 Gerrit-Change-Number: 59913 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 11:40:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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