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Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/1a1bd2a0_e531a74b
PS6, Line 1020: /*
: * Make sure payload/OS can't trigger global reset.
: * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3)
: * prior to transferring control to the OS.
: *
nit: Can this be moved to line#1017?
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61520/comment/8aee6959_26368c65
PS4, Line 501: Function performs
nit: Performs
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 12:
(5 comments)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/61259/comment/7f9f28c0_028ce628
PS12, Line 15: GPP_CLK_ON, /* GPP clock always on; default */
nit: inconsistent use of tabs and spaces in this enum.
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/cf5700a2_84926649
PS12, Line 19: #include <device/device.h>
It'd be good to alphabetize the global imports (even though it's not fully alphabetized as is).
https://review.coreboot.org/c/coreboot/+/61259/comment/2a3302b2_02895823
PS12, Line 158: const fsp_dxio_descriptor *dxio_descs = NULL;
Move declarations before logic.
https://review.coreboot.org/c/coreboot/+/61259/comment/ee6a3a96_50b372ea
PS12, Line 164: if (dxio_descs != NULL) {
Is it an error if dxio_descs == NULL?
https://review.coreboot.org/c/coreboot/+/61259/comment/0db3aa6f_60984137
PS12, Line 173: if (clk_req == CLK_DISABLE || clk_req == CLK_ENABLE)
nit: clk_req != GPP_CLK_REQ
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Change subject: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support
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Patch Set 1: Code-Review+1
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Change subject: vc/amd/cezanne: Add support to map UARTs
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
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Patch Set 8: Code-Review+1
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Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
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Patch Set 9: Code-Review+2
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Change subject: mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support
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Patch Set 1: Code-Review+2
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 11:
(2 comments)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/61020/comment/eb0baa9c_2d4cfd88
PS11, Line 9: #include <soc/soc_chip.h>
> Since every SoC won't have soc_chip.h, compilation issue is seen. Need to remove this line.
#include "chip.h" instead #include <soc/soc_chip.h>
refer to src/drivers//uart/acpi/acpi.c file
https://review.coreboot.org/c/coreboot/+/61020/comment/f6003f26_d4a8e7de
PS11, Line 152: static void wifi_dsm_ddrrfim_func3_cb(void *ptr)
> You can create a weak function here (example: get_wifi_sar_limits), which returns default value (0) […]
I believe this code need little more generalisation (refer to src/drivers//uart/acpi/acpi.c) about getting information from platform. assumptions for having config_of_soc() from common driver code is not scalable (IMO)
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Change subject: soc/amd/common/block/psp: add PSP command
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Patch Set 8: Code-Review+1
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