coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Add probes for stylus and camera
by Evan Green (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: SH Kim, Tim Wawrzynczak, Edward Doan, Karthik Ramasubramanian. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61618 ) Change subject: mb/google/dedede/var/bugzzy: Add probes for stylus and camera ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Tim, would you be able to take a look while Karthik's out? Regarding the overloading of the STYLUS_PRESENT, I'm not a huge expert on the FW_CONFIG bits, but is there a model-specific section of bits where you could actually define the true meaning of this bit? -- To view, visit https://review.coreboot.org/c/coreboot/+/61618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42a63976b9521844f64180b550b16bac344f37 Gerrit-Change-Number: 61618 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:14:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: mb/google/brya: Update Type-C USB2 port configuration ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/include/soc/usb.h: PS4: > Can we please split out the mainboard changes from the SoC changes? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: Fixup variant GPIOs
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61585 ) Change subject: mb/google/cyan: Fixup variant GPIOs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Relm has been tested, Wizpig has not, but AFAICT the audio config is exactly the same for all varian […] 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/61585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea Gerrit-Change-Number: 61585 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: CoolStar Organization <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:01:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 8: (3 comments) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/61462/comment/276be1f6_df621313 PS8, Line 125: u32 soc_read_c2p38(void) since all bit combinations might be valid here, the return value can't be used for both success/error and register value returning. i'd use this implementation instead that doesn't have this possible problem https://review.coreboot.org/c/coreboot/+/60968/11/src/soc/amd/common/block/… https://review.coreboot.org/c/coreboot/+/61462/comment/9a138d8f_cadf8f39 PS8, Line 147: if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) { this condition is also true in the error case of the soc_read_c2p38 call https://review.coreboot.org/c/coreboot/+/61462/comment/bdd8d204_588c653e PS8, Line 152: printk(BIOS_DEBUG, "PSP: Fuse SPL not requested\n"); this needs to be put in curly brackets, since the code in the corresponding if statement is in curly brackets -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 8 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot/secdata_tpm: Set up space for widevine counter info
by Mohan Viswanathan (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Andrey Pronin, Raul Rangel, Name of user not set #1004133, Jon Murphy, Paul Menzel, Julius Werner, Rob Barnes, Yu-Ping Wu, Karthik Ramasubramanian. Mohan Viswanathan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61521 ) Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Okay, I'm not sure why this needs to be so complicated but I'll trust you on that I guess. […] I do not see any issues arising from power loss to the counters; probably we may miss a counter increment by not being able to commit the value to NV RAM due to random power loss. May be Andrey can comment further if i missed something. -- To view, visit https://review.coreboot.org/c/coreboot/+/61521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80de9024195452a235cbed73e21410f848c91722 Gerrit-Change-Number: 61521 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Name of user not set #1004133 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 15:57:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mohan Viswanathan Comment-In-Reply-To: Name of user not set #1004133 Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update USB2_PORT_MAX macro
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61623 ) Change subject: soc/intel/alderlake: Update USB2_PORT_MAX macro ...................................................................... soc/intel/alderlake: Update USB2_PORT_MAX macro The patch updates USB2_PORT_MAX macro to allow mark type_c flag and also also renames the macro to USB2_PORT_MAX_TYPE_C to reflect the USB2 port is mapped to Type-C. BUG=b:193287279 TEST=Build the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I464f139d8e367907191c04f9170ac53d327776ee --- M src/soc/intel/alderlake/include/soc/usb.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/1 diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 70a367e..0d19a13 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -94,14 +94,15 @@ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ } -/* Max TX and Pre-emp settings */ -#define USB2_PORT_MAX(pin) { \ +/* Type-C Port, Max TX and Pre-emp settings */ +#define USB2_PORT_MAX_TYPE_C(pin) { \ .enable = 1, \ .ocpin = (pin), \ .tx_bias = USB2_BIAS_56P3MV, \ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } /* Type-C Port, no BC1.2 charge detect module / MUX -- To view, visit https://review.coreboot.org/c/coreboot/+/61623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464f139d8e367907191c04f9170ac53d327776ee Gerrit-Change-Number: 61623 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Update Type-C USB2 port configuration
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Maulik V Vaghela, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph. Hello build bot (Jenkins), Anil Kumar K, Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61586 to look at the new patch set (#5). Change subject: mb/google/brya: Update Type-C USB2 port configuration ...................................................................... mb/google/brya: Update Type-C USB2 port configuration The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in the device tree. The macro modifies the USB2 configuration to indicate the port mapped to Type-C and sets Max TX and Pre-emp settings. The change is required to enable port reset event on the USB2 port#2. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. The change is done for Gimble DVT and EVT boards. BUG=b:193287279 TEST=Built coreboot for Gimble and tested type A pen drive detect as super speed device on both the Type-C ports. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Rework Makefile
by Sean Rhodes (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61620 to look at the new patch set (#10). Change subject: payloads/tianocore: Rework Makefile ...................................................................... payloads/tianocore: Rework Makefile Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This includes 3 new options: * TIANOCORE_BOOT_MANAGER_ESCAPE * TIANOCORE_HAVE_EFI_SHELL * TIANOCORE_FOLLOW_BGRT_SPEC This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61620/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/61620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Gerrit-Change-Number: 61620 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2C
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61592 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2C ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2C Sabrina uses an identical I2C controller as Picasso and Cezanne. Also both the type and version read-only register of the I2C controller contain identical values. The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are defined in the dw_i2c_regs struct in the common Designware I2C code aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since common DW I2C code doesn't access those, this is no problem. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index c24f1a3..2c54f61 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -51,7 +51,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c Gerrit-Change-Number: 61592 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/designware/dw_i2c: improve CONTROL_SPEED_FS definition
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61591 ) Change subject: drivers/i2c/designware/dw_i2c: improve CONTROL_SPEED_FS definition ...................................................................... drivers/i2c/designware/dw_i2c: improve CONTROL_SPEED_FS definition The speed control bits of the Designware I2C controller are bits 1 and 2 in the control register, so the values should be written as number shifted by the number of the first bit. The resulting constant is identical. TEST=Timeless build for amd/chausie results in identical binary Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id0881dfcd7703ab6a70a9b1a355d5a93771aebc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 2a7c6fc..2cc236e 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -43,7 +43,7 @@ enum { CONTROL_MASTER_MODE = (1 << 0), CONTROL_SPEED_SS = (1 << 1), - CONTROL_SPEED_FS = (1 << 2), + CONTROL_SPEED_FS = (2 << 1), CONTROL_SPEED_HS = (3 << 1), CONTROL_SPEED_MASK = (3 << 1), CONTROL_10BIT_SLAVE = (1 << 3), -- To view, visit https://review.coreboot.org/c/coreboot/+/61591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0881dfcd7703ab6a70a9b1a355d5a93771aebc6 Gerrit-Change-Number: 61591 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022