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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 12:
(1 comment)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/352b3ebc_34bf391b
PS12, Line 173: if (clk_req == CLK_DISABLE || clk_req == CLK_ENABLE)
> nit: clk_req != GPP_CLK_REQ
nm, I was looking at the wrong enum.
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Change subject: console: Add compile-time fast path when only CBMEM console is used
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Patch Set 3: Code-Review+2
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Change subject: console: Add loglevel marker codes to stored consoles
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File util/cbmem/cbmem.c:
https://review.coreboot.org/c/coreboot/+/61308/comment/693f4584_acbae03a
PS7, Line 788: BIOS_LOG_IS_MARKER
I'll need to filter out the marker bytes in `cbmem_dump_console_to_uart`.
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Change subject: console: Add ANSI escape sequences for highlighting
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Patch Set 6: Code-Review+2
(1 comment)
File src/commonlib/include/commonlib/loglevel.h:
https://review.coreboot.org/c/coreboot/+/61307/comment/7c81f9d7_a6db7042
PS6, Line 192: BIOS_LOG_ANSI_ESCAPE_CHAR
No longer needed
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Change subject: console: Add loglevel prefix to interactive consoles
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Patch Set 6: Code-Review+2
(2 comments)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/61306/comment/6f2f1e21_22d0be30
PS5, Line 80: console_interactive_tx_byte
> Yeah... […]
Yeah, we spend a ton of time just waiting for the UART controller to write a byte, so I don't think a couple function calls will really make a difference. I think it looks pretty clean now.
https://review.coreboot.org/c/coreboot/+/61306/comment/012e579a_731b64b9
PS5, Line 85:
> This was my personal preference choice after playing around with various distances... […]
Ack
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Change subject: mb/google/fizz: update VBT for karma variant
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61625/comment/c64f019c_96426d8e
PS1, Line 12: unexpected
ewww
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Change subject: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/e01c93c7_c50f0f53
PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
> +1 to what Tim mentioned here.
> Correct, cse_is_hfs1_spi_protected() is only required, but not "cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())" . Did i miss something?
Please check ME BWG 3.5.1 para 3 that talks about handling global reset in case of CSE is in error state.
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