coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 ) Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/include/soc/usb.h: PS4: > Oops looks like we can't b/c it won't compile anymore, sorry Sridhar! No problem! -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 18:57:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Maulik V Vaghela, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph. Hello build bot (Jenkins), Anil Kumar K, Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61586 to look at the new patch set (#6). Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config ...................................................................... soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config The patch updates USB2_PORT_MAX macro to allow mark type_c flag and also renames the macro to USB2_PORT_MAX_TYPE_C to reflect the USB2 port is mapped to Type-C. Also, the patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in the device tree of Gimble and Gimble EVT. The macro modifies the USB2 configuration to indicate the port mapped to Type-C and sets Max TX and Pre-emp settings. The change is required to enable port reset event on the USB2 port#2. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. The change is done for Gimble DVT and EVT boards. BUG=b:193287279 TEST=Built coreboot for Gimble and tested type A pen drive detect as super speed device on both the Type-C ports. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/soc/intel/alderlake/include/soc/usb.h 3 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d Gerrit-Change-Number: 61586 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/galileo/reg_access.c: Remove duplicated "ERROR" in log messages
by HAOUAS Elyes (Code Review) 04 Feb '22

04 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61635 ) Change subject: mb/intel/galileo/reg_access.c: Remove duplicated "ERROR" in log messages ...................................................................... mb/intel/galileo/reg_access.c: Remove duplicated "ERROR" in log messages Change-Id: I1b4e47cb0f0869ef0a62d1fc6adce4a11ed9b999 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/galileo/reg_access.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/61635/1 diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 9b4df3d..c6d5240 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -18,8 +18,7 @@ step = ctx->step; switch (step->id) { default: - printk(BIOS_ERR, - "ERROR - Unknown register set (0x%08x)!\n", + printk(BIOS_ERR, "Unknown register set (0x%08x)!\n", step->id); ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; break; @@ -48,8 +47,7 @@ step = ctx->step; switch (step->id) { default: - printk(BIOS_ERR, - "ERROR - Unknown register set (0x%08x)!\n", + printk(BIOS_ERR, "Unknown register set (0x%08x)!\n", step->id); ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/61635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4e47cb0f0869ef0a62d1fc6adce4a11ed9b999 Gerrit-Change-Number: 61635 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee/ec.c: Fix log message
by HAOUAS Elyes (Code Review) 04 Feb '22

04 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61634 ) Change subject: mb/google/kahlee/ec.c: Fix log message ...................................................................... mb/google/kahlee/ec.c: Fix log message Change-Id: Ic42d5c05938c060ccaa7b1a260cd584b6e1bb1f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/kahlee/ec.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61634/1 diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 51e0e7f..66a9335 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -39,7 +39,7 @@ ec_ioport_base, ec_ioport_size); status = lpc_set_wideio_range(ec_ioport_base, ec_ioport_size); if (status == WIDEIO_RANGE_ERROR) - printk(BIOS_WARNING, "ERROR: Failed to assign a range\n"); + printk(BIOS_ERR, "Failed to assign a range\n"); else printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic42d5c05938c060ccaa7b1a260cd584b6e1bb1f3 Gerrit-Change-Number: 61634 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61633 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61633/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 9e17e27..7f1f87c 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -54,7 +54,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL - select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Gerrit-Change-Number: 61633 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61632 ) Change subject: nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly ...................................................................... nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly There is no need to have the iommu_set_resources function which only calls pci_dev_set_resources, so assign pci_dev_set_resources directly to the set_resources function pointer field in the iommu_ops struct. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I59c20e61a36fcc11b59d786139b4745ff662e560 --- M src/northbridge/amd/pi/00730F01/iommu.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61632/1 diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index c79ddb5..2de53d0 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -21,14 +21,9 @@ res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, - .set_resources = iommu_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/61632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59c20e61a36fcc11b59d786139b4745ff662e560 Gerrit-Change-Number: 61632 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61631 ) Change subject: nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource ...................................................................... nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource This comment was added with the AMD family 15h Trinity IOMMU support in commit 88ebbeb7e2a914330c869147bacb190b4270532f and looks like a copy of the comment about the subtractive decode ranges in the LPC device. The IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this is also not what the code does. This resource is the MMIO region to configure the IOMMU instead, so fix the comment in all copies of the IOMMU support code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 --- M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/pi/00730F01/iommu.c M src/soc/amd/common/block/iommu/iommu.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61631/1 diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 7af6538..587e737 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -13,7 +13,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index ef478dd..c79ddb5 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -12,7 +12,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 67abe9e..9d4f38e 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -12,7 +12,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * KiB; res->align = log2(res->size); -- To view, visit https://review.coreboot.org/c/coreboot/+/61631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Gerrit-Change-Number: 61631 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop duplicated "ERROR" in log messages
by HAOUAS Elyes (Code Review) 04 Feb '22

04 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61630 ) Change subject: drivers/intel/fsp1_1: Drop duplicated "ERROR" in log messages ...................................................................... drivers/intel/fsp1_1: Drop duplicated "ERROR" in log messages Change-Id: I25f56a6f3ca1814666929e91400f52b75a5d607d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c 2 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/61630/1 diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index c74955e..78700a9 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -193,8 +193,7 @@ /* Verify all the HOBs are present */ if (fsp_verification_failure) - printk(BIOS_ERR, - "ERROR - Missing one or more required FSP HOBs!\n"); + printk(BIOS_ERR, "Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ if (CONFIG(DISPLAY_HOBS)) @@ -209,8 +208,7 @@ if ((fsp_memory != NULL) && (cbmem_root != NULL) && (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { fsp_verification_failure = 1; - printk(BIOS_ERR, - "ERROR - FSP reserved memory above CBMEM root!\n"); + printk(BIOS_ERR, "FSP reserved memory above CBMEM root!\n"); } /* Verify that the FSP memory was properly reserved */ @@ -218,7 +216,7 @@ (fsp_memory->PhysicalStart != (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; - printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); + printk(BIOS_ERR, "Reserving FSP memory area!\n"); if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { size_t delta_bytes = smm_base diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dcb32c7..d85ba7c 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -20,7 +20,7 @@ /* Verify the HOBs */ if (hob_list_ptr == NULL) { - printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); + printk(BIOS_ERR, "HOB pointer is NULL!\n"); return; } @@ -41,8 +41,7 @@ !get_next_guid_hob(&graphics_info_guid, hob_list_ptr) && CONFIG(DISPLAY_HOBS)) { printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); - printk(BIOS_ERR, - "ERROR - Missing one or more required FSP HOBs!\n"); + printk(BIOS_ERR, "Missing one or more required FSP HOBs!\n"); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/61630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f56a6f3ca1814666929e91400f52b75a5d607d Gerrit-Change-Number: 61630 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/dram/ddr2.c: Fix log messages
by HAOUAS Elyes (Code Review) 04 Feb '22

04 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61629 ) Change subject: device/dram/ddr2.c: Fix log messages ...................................................................... device/dram/ddr2.c: Fix log messages Change 'printk(BIOS_WARNING, "ERROR:' to printk(BIOS_ERR, "'. Change-Id: Id25bdb1e6b6d7085eff9c2be8263223a91dff061 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/61629/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 0eba0e3..2ade8ef 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -322,13 +322,13 @@ printram("SPD contains 0x%02x bytes\n", spd_size); if (spd_size < 64 || eeprom_size < 64) { - printk(BIOS_WARNING, "ERROR: SPD to small\n"); + printk(BIOS_ERR, "SPD too small\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { - printk(BIOS_WARNING, "ERROR: SPD checksum error\n"); + printk(BIOS_ERR, "SPD checksum error\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_CRC_ERROR; } @@ -336,8 +336,7 @@ reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { - printk(BIOS_WARNING, - "ERROR: Unsupported SPD revision %01x.%01x\n", + printk(BIOS_ERR, "Unsupported SPD revision %01x.%01x\n", reg8 >> 4, reg8 & 0xf); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; @@ -348,7 +347,7 @@ reg8 = spd[2]; printram(" Type : 0x%02x\n", reg8); if (reg8 != 0x08) { - printk(BIOS_WARNING, "ERROR: Unsupported SPD type %x\n", reg8); + printk(BIOS_ERR, "Unsupported SPD type %x\n", reg8); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25bdb1e6b6d7085eff9c2be8263223a91dff061 Gerrit-Change-Number: 61629 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/8a0b44b1_88969b88 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) > didn't get u ? Only BIOS should have capability to trigger global reset and sending GLOBAL RESET MEI message. Recommendations as follow: 1. BIOS should send GLOBAL RESET MEI command if CSE is not in error state and not sent EOP command before. This is to avoid the synchronization issues between host and CSE. 2. If CSE is in error state, *BIOS* should trigger global reset by setting PCH register(I/O 0xCF9 write of 06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR). 3. If FWSTS1[4] (non-production environment) is set, allow OS to trigger global reset by setting the PCH register(as said in Point#2) . In this scenario, BIOS shouldn't lock global reset config. -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 18:36:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2022