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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 11:
(3 comments)
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/cd7d82a8_02a01ec3
PS8, Line 125: u32 soc_read_c2p38(void)
> since all bit combinations might be valid here, the return value can't be used for both success/erro […]
Done
https://review.coreboot.org/c/coreboot/+/61462/comment/2ef441b9_604d9c65
PS8, Line 147: if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) {
> this condition is also true in the error case of the soc_read_c2p38 call
Done
https://review.coreboot.org/c/coreboot/+/61462/comment/f33f05cd_92430daf
PS8, Line 152: printk(BIOS_DEBUG, "PSP: Fuse SPL not requested\n");
> this needs to be put in curly brackets, since the code in the corresponding if statement is in curly […]
Done
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is requred. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=Test on guybrush that PSP receives message.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
3 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/11
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is requred. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=Test on guybrush that PSP receives message.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
3 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/10
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 9:
(1 comment)
File src/soc/amd/common/block/psp/psp_gen2.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140033):
https://review.coreboot.org/c/coreboot/+/61462/comment/58a7ac3e_2edb065e
PS9, Line 150: printk(BIOS_ERR, "PSP: Failed to read psp base adddress.\n");
'adddress' may be misspelled - perhaps 'address'?
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to look at the new patch set (#9).
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is requred. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=Test on guybrush that PSP receives message.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
3 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/9
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61579 )
Change subject: mb/google/fizz: update VBT for karma variant
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61579/comment/8fbe051f_163013f9
PS1, Line 11:
> Any idea what the difference is, or what is fixed? From what version was the current VBT?
No idea on any of those unfortunately.
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Change subject: mb/google/cyan: Fix variant GPIOs
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61585/comment/a65a510c_ed7a8bd9
PS1, Line 7: Fixup
> Fix up
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/cyan: Fix variant GPIOs
......................................................................
mb/google/cyan: Fix variant GPIOs
- set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio
- set GPSW-37 to NC for all variants (not used for LPE audio)
- set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio
- set GPSE-77 as maskable on variant using Maxim audio, to match mask setting
for jack detect GPIO on other variants
- set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to
change in cherryview pinctrl driver circa kernel v3.18 which no longer masks
all interrupts at init)
Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/cyan/variants/banon/gpio.c
M src/mainboard/google/cyan/variants/celes/gpio.c
M src/mainboard/google/cyan/variants/cyan/gpio.c
M src/mainboard/google/cyan/variants/edgar/gpio.c
M src/mainboard/google/cyan/variants/kefka/gpio.c
M src/mainboard/google/cyan/variants/reks/gpio.c
M src/mainboard/google/cyan/variants/relm/gpio.c
M src/mainboard/google/cyan/variants/setzer/gpio.c
M src/mainboard/google/cyan/variants/terra/gpio.c
M src/mainboard/google/cyan/variants/ultima/gpio.c
M src/mainboard/google/cyan/variants/wizpig/gpio.c
11 files changed, 20 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/61585/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 )
Change subject: soc/intel/alderlake: Inject CSE TS into timestamp_table
......................................................................
Patch Set 12: Code-Review+2
(1 comment)
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/59507/comment/dbf56f3f_e242380f
PS7, Line 9: ramstage
> > Eventually it would be nice though to call it later, as it seems it has potential timestamps for e […]
Sounds like it's working in romstage now.
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