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Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6:
c
File src/soc/intel/alderlake/include/soc/usb.h:
https://review.coreboot.org/c/coreboot/+/61586/comment/cae71c40_898a23c2
PS6, Line 98: #define USB2_PORT_MAX_TYPE_C(pin) { \
: .enable = 1, \
: .ocpin = (pin), \
: .tx_bias = USB2_BIAS_56P3MV, \
: .tx_emp_enable = USB2_PRE_EMP_ON, \
: .pre_emp_bias = USB2_BIAS_56P3MV, \
: .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
: .type_c = 1, \
: }
:
I guess we could split this into two macros,
USB2_PORT_MAX_TYPE_C
and
USB2_PORT_MAX
which could be done in separate CLs. WDYT?
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Change subject: mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARS
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61217/comment/2f5bb33b_ab985007
PS1, Line 12: will may
NIT - pick one 😊
File src/mainboard/google/brya/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/61217/comment/621cb6e1_a33e79ce
PS1, Line 10: PCIEXP_SUPPORT_RESIZABLE_BARS
NIT - might as well alphabetize this one like you did with DRIVERS_I2C_MAX98390.
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Change subject: mb/google/octopus,reef: Align SMMSTORE region in default.fmd
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> I'm trying to remember why the specifying the start address here is even needed, given that it would […]
yeah should be `0x200000` if I did my math right
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Change subject: mb/google/brya/var/kano: adjust I2C3 speed
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitigation
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 12:
(1 comment)
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/a6caa104_9ce93cd6
PS12, Line 154: CORE_2_PSP_MSG_38_FUSE_SPL
I'm not sure if this is correct for all APUs/CPUs that use the second generation of the PSP mailbox interface
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Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61349/comment/0b3ca471_05cc27bd
PS7, Line 13: TEST
> Can you do a TIMELESS build as well and verify nothing changes?
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61349/comment/a70da850_d5926971
PS7, Line 285: AMD_FW_AB_POSITION
> Why is this declared again?
Copy and paste mistake.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
---
M src/mainboard/google/zork/Kconfig
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
M src/soc/amd/sabrina/Makefile.inc
5 files changed, 34 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/9
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Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is requred. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=Test on guybrush that PSP receives message.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
3 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61462/12
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