coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
7066 discussions

Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Cliff Huang (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 10: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61354/comment/ffe6520c_37962c84 PS10, Line 11: > It would be good to mention the explicit dependency on having a […] will add: build dependency: soc/intel/common/block/pcie/rtd3 This driver will use the rtd3 methods for the same parent in the device tree. The rtd3 chip needs to be added on the same root port in the devicetree separately. File src/drivers/wwan/fm/Kconfig: https://review.coreboot.org/c/coreboot/+/61354/comment/5d0d254f_8ab331ab PS10, Line 9: > Right now there is an explicit dependency on also having a […] Yes. it depends on rtd3 chip to be selected to build this driver. it is supposed to point to the same rtd3 chip driver on the same parent for the rtd3 method provided only from this particular instance. This driver does not need to know about its root port number, or it is on CPU or PCH root port. when it calls rtd3 methods, the rtd3 drive takes care of root port specific. File src/drivers/wwan/fm/acpi_fm350gl.c: https://review.coreboot.org/c/coreboot/+/61354/comment/b3690b61_3006d1d2 PS10, Line 103: : /* : Generate second half reset flow (SHRF) method. : */ > ``` […] will fix. File src/drivers/wwan/fm/chip.h: https://review.coreboot.org/c/coreboot/+/61354/comment/02f0e006_fe774272 PS10, Line 21: RTD3 > It points to the RP right? maybe: […] This needs to point to the chip soc/intel/common/block/pcie/rtd3 on the same root port. This is passed so it can reference to rtd3 config for the 'ext_pm_support'. Please also see the https://review.coreboot.org/c/coreboot/+/61355 for how it is referenced. -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:47:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: spd/lp5: Generate initial SPDs for Sabrina SoC
by Karthik Ramasubramanian (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61543 ) Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I've added a new part in CB:61442 so you'll probably need to rebase (it should be submitted soon bec […] Rebased and included the new SPD. -- To view, visit https://review.coreboot.org/c/coreboot/+/61543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Gerrit-Change-Number: 61543 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:46:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/spd_tools/spd_gen/lp5: Update BusWidth Encoding
by Karthik Ramasubramanian (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Reka Norman. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61639 ) Change subject: util/spd_tools/spd_gen/lp5: Update BusWidth Encoding ...................................................................... util/spd_tools/spd_gen/lp5: Update BusWidth Encoding ADL and Sabrina have different advisory regarding encoding the bus width. Encode the bus width as per the respective advisories. BUG=b:211510456 TEST=Build spd_gen and ensure that the bus width is encoded as expected. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25 --- M util/spd_tools/src/spd_gen/lp5.go 1 file changed, 28 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/61639/1 diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index 22927b2..1db5b8d 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -57,6 +57,7 @@ type LP5Set struct { SPDRevision byte + busWidthEncoding byte } /* ------------------------------------------------------------------------------------------ */ @@ -137,14 +138,6 @@ */ LP5SPDValueOptionalFeatures = 0x08 - /* - * For ADL (as per advisory #616599): - * 7:5 (Number of system channels) = 000 (1 channel always) - * 4:3 (Bus width extension) = 00 (no ECC) - * 2:0 (Bus width) = 001 (x16 always) - * Set to 0x01. - */ - LP5SPDValueBusWidth = 0x01 /* * From JEDEC spec: @@ -191,9 +184,25 @@ var LP5SetInfo = map[int]LP5Set{ 0: { SPDRevision: LP5SPDValueRevision1_0, + /* + * For ADL (as per advisory #616599): + * 7:5 (Number of system channels) = 000 (1 channel always) + * 4:3 (Bus width extension) = 00 (no ECC) + * 2:0 (Bus width) = 001 (x16 always) + * Set to 0x01. + */ + busWidthEncoding: 0x01, }, 1: { SPDRevision: LP5SPDValueRevision1_1, + /* + * For Sabrina (as per advisory b/211510456): + * 7:5 (Number of system channels) = 000 (1 channel always) + * 4:3 (Bus width extension) = 00 (no ECC) + * 2:0 (Bus width) = 010 (x32 always) + * Set to 0x02. + */ + busWidthEncoding: 0x02, }, } @@ -306,7 +315,7 @@ LP5SPDIndexPackageType: {getVal: LP5EncodePackageType}, LP5SPDIndexOptionalFeatures: {constVal: LP5SPDValueOptionalFeatures}, LP5SPDIndexModuleOrganization: {getVal: LP5EncodeModuleOrganization}, - LP5SPDIndexBusWidth: {constVal: LP5SPDValueBusWidth}, + LP5SPDIndexBusWidth: {getVal: LP5EncodeBusWidth}, LP5SPDIndexTimebases: {constVal: LP5SPDValueTimebases}, LP5SPDIndexTCKMin: {getVal: LP5EncodeTCKMin}, LP5SPDIndexTCKMinFineOffset: {getVal: LP5EncodeTCKMinFineOffset}, @@ -409,6 +418,16 @@ return b } +func LP5EncodeBusWidth(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.busWidthEncoding +} + func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte { return convPsToMtbByte(memAttribs.TCKMinPs) } -- To view, visit https://review.coreboot.org/c/coreboot/+/61639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25 Gerrit-Change-Number: 61639 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: spd/lp5: Generate initial SPDs for Sabrina SoC
by Karthik Ramasubramanian (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Reka Norman, Reka Norman, Nick Vaccaro, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61543 to look at the new patch set (#3). Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC ...................................................................... spd/lp5: Generate initial SPDs for Sabrina SoC Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 --- M spd/lp5/platforms_manifest.generated.txt A spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-1.hex A spd/lp5/set-1/spd-2.hex A spd/lp5/set-1/spd-3.hex A spd/lp5/set-1/spd-empty.hex 6 files changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/61543/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Gerrit-Change-Number: 61543 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/lapic: Support switching to X2APIC mode
by Kyösti Mälkki (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55262 ) Change subject: cpu/x86/lapic: Support switching to X2APIC mode ...................................................................... Patch Set 16: (1 comment) Patchset: PS8: > Right, I cherry-picked the commits atop master. I'll test with a checkout instead. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9 Gerrit-Change-Number: 55262 Gerrit-PatchSet: 16 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:44:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Mark the WWAN device as an UntrustedDevice
by Nick Vaccaro (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, EricR Lai. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61628 ) Change subject: mb/google/brya: Mark the WWAN device as an UntrustedDevice ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e Gerrit-Change-Number: 61628 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:40:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Robert Zieba, Raul Rangel, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 13: (3 comments) File src/soc/amd/cezanne/fch.c: PS13: without having looked into the details: can the newly added code in gpp_clk_setup be factored out into a separate function? https://review.coreboot.org/c/coreboot/+/61259/comment/eda34e4f_8173e6b6 PS13, Line 11: #include "chip.h" i think coreboot usually puts the "" includes after the <> includes. reordering includes should be done in a separate patch File src/soc/amd/cezanne/platform_descriptors.c: PS13: i'd add the port descriptors of all boards to their ramstage instead of introducing a weak function here. the solution with the weak function would also result in having different dxio descriptor data in romstage and ramstage which makes things much more difficult to debug -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by Nick Vaccaro (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... Patch Set 2: (2 comments) File src/drivers/pcie/generic/Kconfig: https://review.coreboot.org/c/coreboot/+/61627/comment/b3be6807_70bbcc19 PS1, Line 8: used by indicate to : the operating system that maybe "used by the operating system to indicate that" ? File src/drivers/pcie/generic/generic.c: https://review.coreboot.org/c/coreboot/+/61627/comment/fb79264d_127f9095 PS1, Line 20: dev Given you're going to check dev for null, it's safer to check this before dereferencing it on line 17 above. -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/graphics: Create Kconfig for mapping graphic memory base
by Wonkyu Kim (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 ) Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/61389/comment/e80b7cdb_3c84ba87 PS13, Line 128: memory_base = memory_base + CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET; > > GTT size is considered in CONFIG_SOC_INTEL_GFX_MEMBASE_OFFSET. […] We checked GFX team and found that GFX need to use fixed GTT size for new platform while current FSP has UPD for GTT size. After we internal sync up, we got info that FSP will be updated (remove upd for gtt size) So, current constant offset should be ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/61389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Gerrit-Change-Number: 61389 Gerrit-PatchSet: 17 Gerrit-Owner: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/cse_serger: Add component fixed size parameter
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59765 ) Change subject: util/cse_serger: Add component fixed size parameter ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59765/comment/827cca66_acdcc8eb PS5, Line 11: nit: Can we describe what happens when the size is set to be bigger or smaller than the passed-in component? -- To view, visit https://review.coreboot.org/c/coreboot/+/59765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf001bf220c1ccfb189cc4ffa695733400e9c66f Gerrit-Change-Number: 59765 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:36:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2022