coreboot-gerrit February 2022

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61641 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART Sabrina is compatible with the common AMD UART block and also with the DRIVERS_UART_8250MEM_32 driver it selects. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/61641/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 7f1f87c..43c96c0 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -70,7 +70,7 @@ select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Gerrit-Change-Number: 61641 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Add support for Denverton Soc
by Martin Roth (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Felix Singer, Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio, Michal Motyl, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60830 ) Change subject: util/ifdtool: Add support for Denverton Soc ...................................................................... Patch Set 13: Code-Review+2 (2 comments) File util/ifdtool/ifdtool.h: https://review.coreboot.org/c/coreboot/+/60830/comment/e5bd9d9f_2c3f00db PS13, Line 52: PLATFORM_ADL, Not a big deal, but generally the preference is to make changes like reordering things in a separate commit than other code changes. I won't ask for it here, but in the future, it's a good practice. It just makes it more difficult to review when you not only add something, but change the order as well. File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/60830/comment/8a176a3f_1b96c4c9 PS13, Line 718: has_gbe_region = (platform != PLATFORM_DNV); : has_ec_region = (ifd_version >= IFD_VERSION_2) && (platform != PLATFORM_DNV); : has_10gbe_0_region = (platform == PLATFORM_DNV); : has_10gbe_1_region = (platform == PLATFORM_DNV); Would it be useful to turn these into functions or macros so that they can be called from anywhere? If so, that can be changed in a follow-on patch, and doesn't need to be done in this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Gerrit-Change-Number: 60830 Gerrit-PatchSet: 13 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 23:32:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3
by Raul Rangel (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Christian Walter, Felix Held. Hello Jason Glenesk, Marshall Dawson, Christian Walter, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61640 to look at the new patch set (#2). Change subject: WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3 ...................................................................... WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3 This is a WIP of calling the TPM from the S0i3 SMI handler. Notes: * We need to increase the SMM code size const since adding the TPM code into SMM pushes it over the limit. * We should add a mainboard specific hook into elog/gsmi.c that can be used to call tlcl_cr50_disable_deep_sleep. * We need to check if the I2C controller has been powered off via the AOAC registers. If it has, we should re-initialize it. * Can this SMI handler get called while there is a TPM transaction in flight? Sharing hardware between the OS and FW is always very tricky. * I disabled the AOAC for the UART so that the SMM logs get printed to the console. See b/217968734 * What happens if suspend is aborted? Does the SMI handler get called for "resume"? How do we tell the TPM to re-enable deep sleep? The case I'm thinking about is suspend is aborted then we decide to shut down the machine. BUG=b:214479456 TEST=Enter s0i3 on guybrush and see TPM error Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic8eb7ffbe1b5d58eba5c1f94dde8383cd04b1d69 --- M src/cpu/x86/smm/smm_module_loader.c M src/drivers/elog/gsmi.c M src/drivers/i2c/tpm/Makefile.inc M src/security/tpm/Makefile.inc M src/security/tpm/tss/vendor/cr50/Makefile.inc M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h M src/soc/amd/cezanne/acpi/mmio.asl 8 files changed, 45 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/61640/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8eb7ffbe1b5d58eba5c1f94dde8383cd04b1d69 Gerrit-Change-Number: 61640 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3
by Raul Rangel (Code Review) 04 Feb '22

04 Feb '22

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61640 ) Change subject: WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3 ...................................................................... WIP: guybrush: Call TPM Disable Deep Sleep when entering S0i3 This is a WIP of calling the TPM from the S0i3 SMI handler. Notes: * We need to increase the SMM code size const since adding the TPM code into SMM pushes it over the limit. * We should add a mainboard specific hook into elog/gsmi.c that can be used to call tlcl_cr50_disable_deep_sleep. * We need to check if the I2C controller has been powered off via the AOAC registers. If it has, we should re-initialize it. * Can this SMI handler get called while there is a TPM transaction in flight? Sharing hardware between the OS and FW is always very tricky. * I disabled the AOAC for the UART so that the SMM logs get printed to the console. See b/217968734 BUG=b:214479456 TEST=Enter s0i3 on guybrush and see TPM error Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic8eb7ffbe1b5d58eba5c1f94dde8383cd04b1d69 --- M src/cpu/x86/smm/smm_module_loader.c M src/drivers/elog/gsmi.c M src/drivers/i2c/tpm/Makefile.inc M src/security/tpm/Makefile.inc M src/security/tpm/tss/vendor/cr50/Makefile.inc M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h M src/soc/amd/cezanne/acpi/mmio.asl 8 files changed, 45 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/61640/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 101b7c5..4773021 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -10,7 +10,7 @@ #include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 -#define SMM_CODE_SEGMENT_SIZE 0x10000 +#define SMM_CODE_SEGMENT_SIZE 0x20000 /* FXSAVE area during relocation. While it may not be strictly needed the SMM stub code relies on the FXSAVE area being non-zero to enable SSE instructions within SMM mode. */ diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index ebdde19..68bc02c 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <elog.h> +#include <security/tpm/tss/vendor/cr50/cr50.h> #define GSMI_RET_SUCCESS 0x00 #define GSMI_RET_INVALID_PARAMETER 0x82 @@ -105,8 +106,11 @@ case GSMI_CMD_LOG_S0IX_RESUME: ret = GSMI_RET_SUCCESS; - if (command == GSMI_CMD_LOG_S0IX_SUSPEND) + if (command == GSMI_CMD_LOG_S0IX_SUSPEND) { elog_add_event(ELOG_TYPE_S0IX_ENTER); + tlcl_cr50_disable_deep_sleep(); + printk(BIOS_ERR, "RX: GOING INTO S0i3!!!"); + } else { elog_add_event(ELOG_TYPE_S0IX_EXIT); elog_gsmi_cb_platform_log_wake_source(); diff --git a/src/drivers/i2c/tpm/Makefile.inc b/src/drivers/i2c/tpm/Makefile.inc index 51856fa..7b2be38 100644 --- a/src/drivers/i2c/tpm/Makefile.inc +++ b/src/drivers/i2c/tpm/Makefile.inc @@ -3,6 +3,7 @@ verstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c bootblock-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c postcar-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c +smm-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c @@ -21,5 +22,6 @@ verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c +smm-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c ramstage-$(CONFIG_DRIVER_I2C_TPM_ACPI) += chip.c diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index c36183d..eb07d74 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -37,6 +37,9 @@ bootblock-y += tss/tcg-2.0/tss_marshaling.c bootblock-y += tss/tcg-2.0/tss.c +smm-y += tss/tcg-2.0/tss_marshaling.c +smm-y += tss/tcg-2.0/tss.c + ## TSPI ramstage-y += tspi/tspi.c diff --git a/src/security/tpm/tss/vendor/cr50/Makefile.inc b/src/security/tpm/tss/vendor/cr50/Makefile.inc index 8bacafd..a8b613c 100644 --- a/src/security/tpm/tss/vendor/cr50/Makefile.inc +++ b/src/security/tpm/tss/vendor/cr50/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += cr50.c romstage-y += cr50.c postcar-y += cr50.c +smm-y += cr50.c verstage-$(CONFIG_VBOOT) += cr50.c diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index e38ca30..d499b1f 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -176,3 +176,27 @@ return TPM_SUCCESS; } + +uint32_t tlcl_cr50_disable_deep_sleep(void) +{ + struct tpm2_response *response; + uint16_t cmd = TPM2_CR50_SUB_CMD_DISABLE_DEEP_SLEEP; + + printk(BIOS_DEBUG, "Disabling deep sleep\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &cmd); + + if (!response) + return TPM_E_IOERROR; + + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) + /* Explicitly inform caller when command is not supported */ + return TPM_E_NO_SUCH_COMMAND; + + if (response->hdr.tpm_code) + /* Unexpected return code from Cr50 */ + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 0028e80..f341db7 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -16,6 +16,7 @@ #define TPM2_CR50_SUB_CMD_TPM_MODE (40) #define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52) #define TPM2_CR50_SUB_CMD_RESET_EC (53) +#define TPM2_CR50_SUB_CMD_DISABLE_DEEP_SLEEP (59) /* Cr50 vendor-specific error codes. */ #define VENDOR_RC_ERR 0x00000500 @@ -104,4 +105,11 @@ */ uint32_t tlcl_cr50_reset_ec(void); +/** + * CR50 specific TPM command sequence block entering deep sleep. + * + * Returns TPM_E_* for errors. + */ +uint32_t tlcl_cr50_disable_deep_sleep(void); + #endif /* CR50_TSS_STRUCTURES_H_ */ diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl index 9e587b7..98f27af 100644 --- a/src/soc/amd/cezanne/acpi/mmio.asl +++ b/src/soc/amd/cezanne/acpi/mmio.asl @@ -88,7 +88,7 @@ } } - AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) + // AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/61640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8eb7ffbe1b5d58eba5c1f94dde8383cd04b1d69 Gerrit-Change-Number: 61640 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Cliff Huang (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 10: (2 comments) File src/drivers/wwan/fm/Kconfig: https://review.coreboot.org/c/coreboot/+/61354/comment/6c06812e_06103a4a PS10, Line 9: > Sorry I meant can you add something about that in the help text? will do. File src/drivers/wwan/fm/chip.h: https://review.coreboot.org/c/coreboot/+/61354/comment/b5f9b561_487ab1a3 PS10, Line 21: RTD3 > Sorry meant to erase that comment once I figured it out No problem. I think I was not clear about adding such reference. Supposed we have two devices; one on CPU RP; and the other one PCH RP. And they all use rtd3 methods. Each device can reference its corresponding rtd3 instance config specified from the devicetree so that they knows what rtd3 methods are available to them. In CPU case, no modPHY power gate support, while PCH one does. -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 23:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Merge gpio table before configuration
by Nick Vaccaro (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Angel Pons, EricR Lai, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61110 ) Change subject: mb/google/brya: Merge gpio table before configuration ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/61110/comment/9d5208f4_76dbc12a PS7, Line 16: struct pad_config *variant_gpio_override_table(size_t *num); Why is it necessary to remove const from variant_gpio_override_table() prototype? -- To view, visit https://review.coreboot.org/c/coreboot/+/61110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I595e7587765df663d1e2fa67efcef9b44c526dd0 Gerrit-Change-Number: 61110 Gerrit-PatchSet: 7 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:56:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Paul Menzel, Thejaswani Putta. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 10: (1 comment) File src/drivers/wwan/fm/Kconfig: https://review.coreboot.org/c/coreboot/+/61354/comment/4718b953_315353a2 PS10, Line 9: > Yes. it depends on rtd3 chip to be selected to build this driver. […] Sorry I meant can you add something about that in the help text? -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:56:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Paul Menzel, Thejaswani Putta. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 10: (1 comment) File src/drivers/wwan/fm/chip.h: https://review.coreboot.org/c/coreboot/+/61354/comment/aff0cb1e_1a490b9f PS10, Line 21: RTD3 > This needs to point to the chip soc/intel/common/block/pcie/rtd3 on the same root port. […] Sorry meant to erase that comment once I figured it out -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:56:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
by Cliff Huang (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61353 to look at the new patch set (#8). Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control - Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - OFSK is used to skip _OFF Method at the end of device driver removal. - ONSK is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device increments OFSK in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees OFSK and skips current execution and decrements OFSK so that _OFF will be executed normally next time. 6. _OFF increments ONSK to skip the following _ON invoked by OSPM. 7. Device driver is reloaded by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees ONSK and skip current execution and decrements ONSK so that _ON will be executed normally next time. - In normal case: When suspend, OSPM invokes _OFF. Since OFSK is zero, the device goes to deeper state as expected. When resume, OSPM invokes _ON. Sinc ONSK is zero, the device goes to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (ONSK, Zero) Name (OFSK, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { ... } Else { ONSK-- } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((OFSK == Zero)) { ... } Else { OFSK-- ONSK++ } } Test: Enable and verify OFSK and ONSK Name objects and the if-condition logic inside _OFF and _ON methods is added. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61353/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/lapic: Fix choice X2APIC_ONLY
by Kyösti Mälkki (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Nico Huber, Wonkyu Kim, Tim Wawrzynczak, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60213 ) Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60213/comment/93e1a8a9_a0164e15 PS2, Line 11: avoid entering a printk() and acquiring console_lock and : dead-locking. > Oh yeah I see, hm, I guess there is the local_irq_restore() which has a compiler-only memory barrier […] Ack File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/60213/comment/992c8722_e5e7f14f PS2, Line 652: lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); > Well, there is LAPIC ICR Destination Shorthand for "ALL LAPIC" and if we ever used it, it would need […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Gerrit-Change-Number: 60213 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Feb 2022 22:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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