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Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 )
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 15:
(1 comment)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/6dd26aae_aa9c4a22
PS13, Line 11: #include "chip.h"
> i think coreboot usually puts the "" includes after the <> includes. […]
Done
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Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 )
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 14:
(2 comments)
File src/soc/amd/cezanne/fch.c:
PS13:
> without having looked into the details: can the newly added code in gpp_clk_setup be factored out in […]
Done
File src/soc/amd/cezanne/platform_descriptors.c:
PS13:
> i'd add the port descriptors of all boards to their ramstage instead of introducing a weak function […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#15).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 91 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/15
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Attention is currently required from: Hung-Te Lin, Raul Rangel, Frans Hendriks, Mariusz Szafrański, Angel Pons, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph, Erik van den Bogaert, Nico Huber, Marshall Dawson, Lee Leahy, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, Michal Motyl, Felix Held.
Hello Hung-Te Lin, build bot (Jenkins), Raul Rangel, Patrick Georgi, Frans Hendriks, Mariusz Szafrański, Angel Pons, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Erik van den Bogaert, Jason Glenesk, Nico Huber, Lee Leahy, Marshall Dawson, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, Michal Motyl, HAOUAS Elyes, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: treewide: Remove "ERROR: "/"WARN: " prefixes from log messages
......................................................................
treewide: Remove "ERROR: "/"WARN: " prefixes from log messages
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
---
M src/acpi/acpigen.c
M src/arch/arm64/fit_payload.c
M src/arch/x86/acpi_bert_storage.c
M src/arch/x86/tables.c
M src/commonlib/storage/sd_mmc.h
M src/cpu/x86/mtrr/mtrr.c
M src/cpu/x86/smm/tseg_region.c
M src/device/dram/ddr4.c
M src/device/dram/lpddr4.c
M src/device/oprom/realmode/x86.c
M src/device/pci_device.c
M src/device/pnp_device.c
M src/drivers/analogix/anx7625/anx7625.c
M src/drivers/i2c/max98390/max98390.c
M src/drivers/i2c/tpm/cr50.c
M src/drivers/intel/fsp1_1/fsp_relocate.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/pmc_mux/conn/conn.c
M src/drivers/net/atl1e.c
M src/drivers/net/r8168.c
M src/drivers/pc80/rtc/option.c
M src/drivers/spi/tpm/tpm.c
M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
M src/drivers/vpd/vpd.c
M src/drivers/wifi/generic/acpi.c
M src/ec/google/chromeec/ec.c
M src/lib/bootmem.c
M src/lib/cbfs.c
M src/lib/cbmem_stage_cache.c
M src/lib/edid.c
M src/lib/fit.c
M src/lib/fit_payload.c
M src/lib/fmap.c
M src/lib/thread.c
M src/lib/timestamp.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/memory.c
M src/mainboard/google/octopus/romstage.c
M src/mainboard/intel/harcuvar/romstage.c
M src/mainboard/scaleway/tagada/romstage.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/sandybridge/common.c
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/i2c.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/cezanne/smihandler.c
M src/soc/amd/common/block/acpi/bert.c
M src/soc/amd/common/block/acpi/gpio.c
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/block/cpu/mca/mca_bert.c
M src/soc/amd/common/block/cpu/mca/mcax_bert.c
M src/soc/amd/common/block/cpu/noncar/memmap.c
M src/soc/amd/common/block/cpu/smm/smm_helper.c
M src/soc/amd/common/block/gpio/gpio.c
M src/soc/amd/common/block/lpc/espi_util.c
M src/soc/amd/common/block/lpc/spi_dma.c
M src/soc/amd/common/block/pci/amd_pci_util.c
M src/soc/amd/common/block/pm/pmlib.c
M src/soc/amd/common/block/smu/smu.c
M src/soc/amd/common/fsp/dmi.c
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/amd/common/fsp/pci/pci_routing_info.c
M src/soc/amd/common/pi/agesawrapper.c
M src/soc/amd/common/pi/def_callouts.c
M src/soc/amd/common/pi/s3_resume.c
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/soc/amd/common/psp_verstage/vboot_crypto.c
M src/soc/amd/common/vboot/vboot_bootblock.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/i2c.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/picasso/smihandler.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/cavium/cn81xx/cpu.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/broadwell/pch/me_status.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/acpi/acpi_bert.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
M src/soc/intel/common/block/irq/irq.c
M src/soc/intel/common/block/pcie/pcie_helpers.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/thermal/thermal_pci.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/chip.c
M src/soc/mediatek/common/include/soc/msdc.h
M src/soc/mediatek/mt8173/da9212.c
M src/soc/mediatek/mt8173/mt6311.c
M src/soc/mediatek/mt8195/dpm_4ch.c
M src/soc/mediatek/mt8195/dptx.c
M src/soc/mediatek/mt8195/dptx_hal.c
M src/soc/mediatek/mt8195/mt6691.c
M src/soc/nvidia/tegra/usb.c
M src/soc/nvidia/tegra210/dp.c
M src/soc/nvidia/tegra210/dsi.c
M src/soc/nvidia/tegra210/funitcfg.c
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/usb/qmpv3_usb_phy.c
M src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
M src/soc/qualcomm/common/usb/qusb_phy.c
M src/soc/rockchip/common/rk808.c
M src/soc/rockchip/rk3288/crypto.c
M src/soc/rockchip/rk3399/display.c
M src/soc/ti/am335x/mmc.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/intel/bd82x6x/early_me.c
M src/southbridge/intel/bd82x6x/early_me_mrc.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/lynxpoint/early_me.c
M src/superio/nuvoton/nct5104d/superio.c
M src/superio/smsc/lpc47n217/superio.c
M src/superio/smsc/lpc47n227/superio.c
M src/superio/smsc/sch5545/superio.c
M src/vendorcode/eltan/security/verified_boot/vboot_check.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/sar.c
129 files changed, 306 insertions(+), 330 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/61309/13
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Hello build bot (Jenkins), Raul Rangel, Nico Huber, Patrick Georgi, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61308
to look at the new patch set (#10).
Change subject: console: Add loglevel marker codes to stored consoles
......................................................................
console: Add loglevel marker codes to stored consoles
In order to provide the same loglevel prefixes and highlighting that
were recently introduced for "interactive" consoles (e.g. UART) to
"stored" consoles (e.g. CBMEM) but minimize the amont of extra storage
space wasted on this info, this patch will write a 1-byte control
character marker indicating the loglevel to the start of every line
logged in those consoles. The `cbmem` utility will then interpret those
markers and translate them back into loglevel prefixes and escape
sequences as needed.
Since coreboot and userspace log readers aren't always in sync,
occasionally an older reader may come across these markers and not know
how to interpret them... but that should usually be fine, as the range
chosen contains non-printable ASCII characters that normally have no
effect on the terminal. At worst the outdated reader would display one
garbled character at the start of every line which isn't that bad.
(Older versions of the `cbmem` utility will translate non-printable
characters into `?` question marks.)
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc
---
M src/commonlib/include/commonlib/loglevel.h
M src/console/printk.c
M src/lib/cbmem_console.c
M util/cbmem/cbmem.c
4 files changed, 51 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61308/10
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Won Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61571 )
Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> Where did you get the positional information for each variant? […]
Hi Nick, thank you for review. I have added a description and charts regarding the PLD values in go/custompldrequirement. Basically, I traced each port in schematics, searched for it in board layout, and compared it with ports on actual physical device.
Do you think I should add a hw engineer as reviewer to verify these positions?
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Benson Leung, Prashant Malani,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61571
to look at the new patch set (#4).
Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants
......................................................................
mb/google/brya: Add custom PLD fields to devicetree for brya variants
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung(a)google.com>
Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51
---
M src/mainboard/google/brya/variants/anahera/overridetree.cb
M src/mainboard/google/brya/variants/anahera4es/overridetree.cb
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
M src/mainboard/google/brya/variants/kano/overridetree.cb
M src/mainboard/google/brya/variants/primus/overridetree.cb
M src/mainboard/google/brya/variants/primus4es/overridetree.cb
M src/mainboard/google/brya/variants/redrix/overridetree.cb
M src/mainboard/google/brya/variants/redrix4es/overridetree.cb
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko4es/overridetree.cb
11 files changed, 518 insertions(+), 74 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61571/4
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Benson Leung, EricR Lai, Prashant Malani,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61388
to look at the new patch set (#13).
Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es
......................................................................
mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es
For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung(a)google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
2 files changed, 112 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61388/13
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Attention is currently required from: Subrata Banik, Won Chung, Benson Leung, EricR Lai, Prashant Malani.
Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Benson Leung, EricR Lai, Prashant Malani,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61388
to look at the new patch set (#12).
Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es
......................................................................
mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es
For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung(a)google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/brya4es/overridetree.cb
2 files changed, 112 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/61388/12
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