coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61380 to look at the new patch set (#4). Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... soc/inte/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding the coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region. This patch adds support to control CSE firmware update functionality. BUG=b:153410586 TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 --- M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/debug/Kconfig A src/soc/intel/common/block/debug/Makefile.inc A src/soc/intel/common/block/debug/debug_feature.c A src/soc/intel/common/block/include/intelblocks/debug_feature.h 5 files changed, 80 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61380/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Subrata Banik (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/db015e0c_0e49cd79 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) > >**When CSE is always in bad state then how can one follow #2 so the only way is #1 hence, we should avoid locking the PMC cf9.** > > Per the guide, when CSE is in bad state, global reset to be used. Can you please share what is the step to perform the global reset when CSE is in bad state ? and if BIOS lock PMC ETR3 bit 31 without bothering about CSE state using pmc_global_reset_disable_and_lock() (as you have suggested) then how can platform issue global reset ? > Please note OS can't use neither GLOBAL RESET MEI message and global reset PCH register set. The point is platform want to prohibit OS from sending global reset then the lock is required. Ideally the flow would look like this may be 1. Platform is booting and BIOS check the CSE state and MFG mode and if all good then lock the PMC ETR3 knowing that if we still need global reset then MEI message can be used but prohibit OS to trigger global reset using 0xcf9 bit 31. 2. In case, BIOS detects CSE is in bad state then skip locking the CF9 global reset to allow BIOS to perform global reset using 0xcf9 port. Looking at https://elixir.bootlin.com/linux/v5.15.19/source/drivers/platform/x86/intel… code, kernel is actually attempting to set the global reset bit. hence, follow up any cf9 write 0x6/0xe may trigger global reset to host and CSE partition as well. I think we should unconditionally lock the cf9lock irrespective CSE enable or disable. I will address this in next revision. > > I don't see any reason OS wants to use global reset as mentioned in the ME BWG. The section# 3.5.1, we are referring is, guidelines on usage of global reset & GLOBAL RESET MEI message. > > Other section# 3.6.2 refers, when global reset (triggered through setting PCH registers) shouldn't be locked (if HFSTS1[4] is set). -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 14:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/284a9afd_68c38f79 PS2, Line 28: cse_fw_update_disable > > Assumption is, coreboot enables a feature by default and debug logic look for OEM SECTION if the f […] >Also, if I understood it correctly the default value for OEM region is 0xFF so that way, unless someone override it for debug purpose, it would always read as `1` and consider `update is enable` and upon resetting the desire bit for debug purpose (to skip CSE update), the code logic would read it `0`. Not sure if it make sense to refer default `1` as CSE FW update disable. Please note, by default, coreboot gets 0xff if it reads from OEM SECTION. But, the expected value is "1" to enable debug feature. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 13:57:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by build bot (Jenkins) (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140078): https://review.coreboot.org/c/coreboot/+/61380/comment/9dbb6246_5a10f5db PS3, Line 668: if (CONFIG(SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE) && CONFIG(SOC_INTEL_CSE_RW_UPDATE) ) space prohibited before that close parenthesis ')' -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 13:53:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61380 to look at the new patch set (#3). Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... soc/inte/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding the coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region. This patch adds support to control CSE firmware update functionality. BUG=b:153410586 TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 --- M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/debug/Kconfig A src/soc/intel/common/block/debug/Makefile.inc A src/soc/intel/common/block/debug/debug_feature.c A src/soc/intel/common/block/include/intelblocks/debug_feature.h 5 files changed, 80 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61380/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by Angel Pons (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... Patch Set 3: (2 comments) File src/drivers/pcie/generic/generic.c: https://review.coreboot.org/c/coreboot/+/61627/comment/142e41b5_4def4da7 PS3, Line 20: !config You also need to update this https://review.coreboot.org/c/coreboot/+/61627/comment/dbf95ca2_b7e2191f PS3, Line 41: pci_rom_ssdt(dev); This is skipped when `!config->is_untrusted`, is it intentional? -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 05 Feb 2022 13:12:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Sridhar Siricilla (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/9aca85d7_2cbe08f8 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) > > >3rd para says. […] >**When CSE is always in bad state then how can one follow #2 so the only way is #1 hence, we should avoid locking the PMC cf9.** Per the guide, when CSE is in bad state, global reset to be used. Please note OS can't use neither GLOBAL RESET MEI message and global reset PCH register set. I don't see any reason OS wants to use global reset as mentioned in the ME BWG. The section# 3.5.1, we are referring is, guidelines on usage of global reset & GLOBAL RESET MEI message. Other section# 3.6.2 refers, when global reset (triggered through setting PCH registers) shouldn't be locked (if HFSTS1[4] is set). -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:57:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by EricR Lai (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: oh the UUID will be random, never mind :p -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya0 and bry...
by EricR Lai (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Won Chung, Benson Leung, Prashant Malani. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61388 ) Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es ...................................................................... Patch Set 13: Code-Review+2 (1 comment) Patchset: PS13: Just curious, what this for? -- To view, visit https://review.coreboot.org/c/coreboot/+/61388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Gerrit-Change-Number: 61388 Gerrit-PatchSet: 13 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:31:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by EricR Lai (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: hmm, IIRC, the _DSD UUID should be unique what if we put this in another RP? Will that be conflicted? -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:28:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022