coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

1 participants
7066 discussions

Change in coreboot[master]: nb/intel/i945/chip.h: Clean up includes
by HAOUAS Elyes (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Paul Menzel, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61320 ) Change subject: nb/intel/i945/chip.h: Clean up includes ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61320/comment/42f1c924_f1eac2b2 PS1, Line 9: 'i915_gpu_controller_info' needs <drivers/intel/gma/gma.h> instead of : <drivers/intel/gma/i915.h>. : Also add <stdint.h> > Please mark it up as a list. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e32be1e15af13c464a48afb5f5cff270d909c2 Gerrit-Change-Number: 61320 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 22:25:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add custom PLD fields to devicetree for brya0 and bry...
by Subrata Banik (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Won Chung, Benson Leung, Prashant Malani. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61388 ) Change subject: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61388/comment/e9a50aa0_06ba3ec0 PS13, Line 7: mb/google/brya: Add custom PLD fields to devicetree for brya0 and brya4es reached > 72? consider rewriting the title ? -- To view, visit https://review.coreboot.org/c/coreboot/+/61388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Gerrit-Change-Number: 61388 Gerrit-PatchSet: 13 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 19:18:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61633 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 9e17e27..7f1f87c 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -54,7 +54,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL - select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Gerrit-Change-Number: 61633 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61632 ) Change subject: nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly ...................................................................... nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly There is no need to have the iommu_set_resources function which only calls pci_dev_set_resources, so assign pci_dev_set_resources directly to the set_resources function pointer field in the iommu_ops struct. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I59c20e61a36fcc11b59d786139b4745ff662e560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61632 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/northbridge/amd/pi/00730F01/iommu.c 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index c79ddb5..2de53d0 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -21,14 +21,9 @@ res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, - .set_resources = iommu_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, }; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59c20e61a36fcc11b59d786139b4745ff662e560 Gerrit-Change-Number: 61632 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61631 ) Change subject: nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource ...................................................................... nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource This comment was added with the AMD family 15h Trinity IOMMU support in commit 88ebbeb7e2a914330c869147bacb190b4270532f and looks like a copy of the comment about the subtractive decode ranges in the LPC device. The IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this is also not what the code does. This resource is the MMIO region to configure the IOMMU instead, so fix the comment in all copies of the IOMMU support code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/pi/00730F01/iommu.c M src/soc/amd/common/block/iommu/iommu.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 7af6538..587e737 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -13,7 +13,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index ef478dd..c79ddb5 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -12,7 +12,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 67abe9e..9d4f38e 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -12,7 +12,7 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * KiB; res->align = log2(res->size); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Gerrit-Change-Number: 61631 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61626 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO Sabrina is compatible with the common AMD ACPIMMIO function block mapping and access functions. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index b0804c7..9e17e27 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -41,7 +41,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Gerrit-Change-Number: 61626 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61625 ) Change subject: soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions ...................................................................... soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions The PM2 ACPIMMIO region should only be accessed with 8 bit accesses. Using 16 or 32 bit read accesses will return the data from the first byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in only the first byte being written which is both unexpected behavior. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 0 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ae86730..2d632f6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -198,31 +198,11 @@ return read8(acpimmio_pmio2 + reg); } -static inline uint16_t pm2_read16(uint8_t reg) -{ - return read16(acpimmio_pmio2 + reg); -} - -static inline uint32_t pm2_read32(uint8_t reg) -{ - return read32(acpimmio_pmio2 + reg); -} - static inline void pm2_write8(uint8_t reg, uint8_t value) { write8(acpimmio_pmio2 + reg, value); } -static inline void pm2_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_pmio2 + reg, value); -} - -static inline void pm2_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_pmio2 + reg, value); -} - static inline uint8_t acpi_read8(uint8_t reg) { return read8(acpimmio_acpi + reg); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Gerrit-Change-Number: 61625 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table
by Felix Held (Code Review) 05 Feb '22

05 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61624 ) Change subject: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table ...................................................................... soc/amd/common/block/acpimmio/print_reset_status: extend bit name table Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/acpimmio/print_reset_status.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c index 309401e..5ff0412 100644 --- a/src/soc/amd/common/block/acpimmio/print_reset_status.c +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -41,13 +41,15 @@ [20] = "DoFullReset", [21] = "SleepReset", [22] = "KbReset", - [23] = "LtReset", + [23] = "LtReset/ShutdownMsg", [24] = "FailBootRst", [25] = "WatchdogIssueReset", [26] = "RemoteResetFromASF", [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", + [30] = "SdpParityErr", + [31] = "SwSyncFloodFlag", }; printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Gerrit-Change-Number: 61624 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common/basecode/eop: coreboot driver perform EOP operations
by Angel Pons (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/basecode/eop: coreboot driver perform EOP operations ...................................................................... Patch Set 23: (1 comment) File src/soc/intel/common/basecode/eop/eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/c76cc276_e51d3ce0 PS23, Line 20: static void do_eop_operations(void *unused) : { : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) { : /* Step 1 */ : cse_send_end_of_post(); : : /* Step 2 */ : cse_lock_config(); : : /* Step 3 */ : if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { : cse_set_to_d0i3(); : heci1_disable(); : } : } : : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) { : /* Step 4 */ : heci_set_to_d0i3(); : /* Step 5 */ : pmc_clear_pmcon_sts(); : } : } > > Now that CSE device state is independent of hiding (see DISABLE_HECI1_AT_PRE_BOOT Kconfig), we sho […] For CSE and SPI, yes. I'm not sure if the PMC is handled specially, but if it's treated like a regular PCI device then we should also use its device operations. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 23 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 05 Feb 2022 18:54:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h...
by HAOUAS Elyes (Code Review) 05 Feb '22

05 Feb '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61648 ) Change subject: intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h> macros ...................................................................... intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h> macros Change-Id: If4c273477a1e4f50dcfc033611b90cd07a3c2542 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/sandybridge/gma.c 2 files changed, 78 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61648/1 diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index a0325d1..37abd89 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/intel_bios.h> #include <drivers/intel/gma/libgfxinit.h> #include <pc80/vga.h> @@ -70,47 +71,47 @@ printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); /* Setup Digital Port Hotplug */ - reg32 = gtt_read(0xc4030); + reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; - gtt_write(0xc4030, reg32); + gtt_write(PCH_PORT_HOTPLUG, reg32); } /* Setup Panel Power On Delays */ - reg32 = gtt_read(0xc7208); + reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); - gtt_write(0xc7208, reg32); + gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ - reg32 = gtt_read(0xc720c); + reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); - gtt_write(0xc720c, reg32); + gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(0xc7210); + reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; - gtt_write(0xc7210, reg32); + gtt_write(PCH_PP_DIVISOR, reg32); } /* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); + gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); + gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { - gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); + gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); } } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 9d01533..9b67a1d 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -10,6 +10,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -314,19 +315,19 @@ if (is_sandy || cpu_stepping() < IVB_STEP_C0) { /* 1: Enable force wake */ - gtt_write(0xa18c, 0x00000001); - gtt_poll(0x130090, (1 << 0), (1 << 0)); + gtt_write(FORCEWAKE, 0x00000001); + gtt_poll(FORCEWAKE_ACK, (1 << 0), (1 << 0)); } else { - gtt_write(0xa180, 1 << 5); - gtt_write(0xa188, 0xffff0001); - gtt_poll(0x130040, (1 << 0), (1 << 0)); + gtt_write(ECOBUS, FORCEWAKE_MT_ENABLE); + gtt_write(FORCEWAKE_MT, 0xffff0001); + gtt_poll(FORCEWAKE_MT_ACK, (1 << 0), (1 << 0)); } if (is_sandy) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ - reg32 = gtt_read(0x42004); + reg32 = gtt_read(ILK_DISPLAY_CHICKEN2); reg32 |= (1 << 14) | (1 << 15); - gtt_write(0x42004, reg32); + gtt_write(ILK_DISPLAY_CHICKEN2, reg32); } if (!is_sandy) { @@ -384,54 +385,54 @@ gtt_write(0xa080, 0x00000004); /* 6: ECO bits */ - reg32 = gtt_read(0xa180); + reg32 = gtt_read(ECOBUS); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) reg32 |= (1 << 20); - gtt_write(0xa180, reg32); + gtt_write(ECOBUS, reg32); /* 6a: for SnB step D2+ only */ if (is_sandy && cpu_stepping() >= SNB_STEP_D2) { - reg32 = gtt_read(0x9400); - reg32 |= (1 << 7); - gtt_write(0x9400, reg32); + reg32 = gtt_read(GEN6_UCGCTL1); + reg32 |= GEN6_CSUNIT_CLOCK_GATE_DISABLE; + gtt_write(GEN6_UCGCTL1, reg32); - reg32 = gtt_read(0x941c); + reg32 = gtt_read(GEN6_GDRST); reg32 &= 0xf; - reg32 |= (1 << 1); - gtt_write(0x941c, reg32); - gtt_poll(0x941c, (1 << 1), (0 << 1)); + reg32 |= GEN6_GRDOM_RENDER; + gtt_write(GEN6_GDRST, reg32); + gtt_poll(GEN6_GDRST, (1 << 1), (0 << 1)); } if (is_sandy) { /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000000); + gtt_write(GEN7_MISCCPCTL, 0x00000000); } else { reg32 = gtt_read(0x907c); reg32 |= (1 << 16); gtt_write(0x907c, reg32); /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000001); + gtt_write(GEN7_MISCCPCTL, 0x00000001); } /* 7 */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { - gtt_write(0x138128, 0x00000029); /* Mailbox Data */ - gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) - gtt_write(0x138124, 0x8000000a); - gtt_poll(0x138124, (1 << 31), (0 << 31)); + if (gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31))) { + gtt_write(GEN6_PCODE_DATA, 0x00000029); /* Mailbox Data */ + gtt_write(GEN6_PCODE_MAILBOX, 0x80000004); /* Mailbox Cmd for RC6 VID */ + if (gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31))) + gtt_write(GEN6_PCODE_MAILBOX, 0x8000000a); + gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31)); } /* 8 */ - gtt_write(0xa090, 0x00000000); /* RC Control */ - gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ - gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ - gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ - gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ - gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + gtt_write(GEN6_RC_CONTROL, 0x00000000); /* RC Control */ + gtt_write(GEN6_RC1_WAKE_RATE_LIMIT, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(GEN6_RC6_WAKE_RATE_LIMIT, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(GEN6_RC6pp_WAKE_RATE_LIMIT, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(GEN6_RC_EVALUATION_INTERVAL, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(GEN6_RC_IDLE_HYSTERSIS, 0x00000019); /* RC Idle Hysteresis */ /* 9 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ @@ -439,20 +440,20 @@ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ /* 10 */ - gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ - gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ - gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ - gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ - gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + gtt_write(GEN6_RC_SLEEP, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(GEN6_RC1e_THRESHOLD, 0x000003e8); /* RC1e Threshold */ + gtt_write(GEN6_RC6_THRESHOLD, 0x0000c350); /* RC6 Threshold */ + gtt_write(GEN6_RC6p_THRESHOLD, 0x000186a0); /* RC6p Threshold */ + gtt_write(GEN6_RC6pp_THRESHOLD, 0x0000fa00); /* RC6pp Threshold */ /* 11 */ - gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ - gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ - gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ - gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ - gtt_write(0xa068, 0x000186a0); /* RP Up EI */ - gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ - gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ + gtt_write(GEN6_RP_DOWN_TIMEOUT, 0x000f4240); /* RP Down Timeout */ + gtt_write(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); /* RP Interrupt Limits */ + gtt_write(GEN6_RP_UP_THRESHOLD, 0x00015f90); /* RP Up Threshold */ + gtt_write(GEN6_RP_DOWN_THRESHOLD, 0x000186a0); /* RP Down Threshold */ + gtt_write(GEN6_RP_UP_EI, 0x000186a0); /* RP Up EI */ + gtt_write(GEN6_RP_DOWN_EI, 0x000493e0); /* RP Down EI */ + gtt_write(GEN6_RP_IDLE_HYSTERSIS, 0x0000000a); /* RP Idle Hysteresis */ /* * 11a: Enable Render Standby (RC6) @@ -462,7 +463,7 @@ * Unfortunately it does not work reliably on all SKUs so * disable it here and it can be enabled by the kernel. */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ + gtt_write(GEN6_RC_CONTROL, 0x88040000); /* HW RC Control */ /* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ @@ -471,13 +472,13 @@ reg32 >>= 16; reg32 &= 0x7f; reg32 <<= 25; - gtt_write(0xa008, reg32); + gtt_write(GEN6_RPNSWREQ, reg32); /* 13: RP Control */ - gtt_write(0xa024, 0x00000592); + gtt_write(GEN6_RP_CONTROL, 0x00000592); /* 14: Enable PM Interrupts */ - gtt_write(0x4402c, 0x03000076); + gtt_write(GEN6_PMIER, 0x03000076); /* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); @@ -506,59 +507,59 @@ /* 15: Deassert Force Wake */ if (is_sandybridge() || cpu_stepping() < IVB_STEP_C0) { - gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - gtt_poll(0x130090, (1 << 0), (0 << 0)); + gtt_write(FORCEWAKE, gtt_read(FORCEWAKE) & ~1); + gtt_poll(FORCEWAKE_ACK, (1 << 0), (0 << 0)); } else { - gtt_write(0xa188, 0x1fffe); - if (gtt_poll(0x130040, (1 << 0), (0 << 0))) - gtt_write(0xa188, gtt_read(0xa188) | 1); + gtt_write(FORCEWAKE_MT, 0x1fffe); + if (gtt_poll(FORCEWAKE_MT_ACK, (1 << 0), (0 << 0))) + gtt_write(FORCEWAKE_MT, gtt_read(FORCEWAKE_MT) | 1); } /* 16: SW RC Control */ - gtt_write(0xa094, 0x00060000); + gtt_write(GEN6_RC_STATE, 0x00060000); /* Setup Digital Port Hotplug */ - reg32 = gtt_read(0xc4030); + reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; - gtt_write(0xc4030, reg32); + gtt_write(PCH_PORT_HOTPLUG, reg32); } /* Setup Panel Power On Delays */ - reg32 = gtt_read(0xc7208); + reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); - gtt_write(0xc7208, reg32); + gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ - reg32 = gtt_read(0xc720c); + reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); - gtt_write(0xc720c, reg32); + gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(0xc7210); + reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; - gtt_write(0xc7210, reg32); + gtt_write(PCH_PP_DIVISOR, reg32); } /* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); + gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); + gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { - gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); + gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/61648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c273477a1e4f50dcfc033611b90cd07a3c2542 Gerrit-Change-Number: 61648 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2022