coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/common/pmc: Add `finalize` operation for pmc
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61649 ) Change subject: soc/intel/common/pmc: Add `finalize` operation for pmc ...................................................................... soc/intel/common/pmc: Add `finalize` operation for pmc This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 --- M src/soc/intel/common/block/pmc/pmc.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61649/1 diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 560ab9b..e74cfd1 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -8,6 +8,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <soc/pci_devs.h> +#include <soc/pm.h> static void pch_pmc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, @@ -80,6 +81,18 @@ generate_acpi_power_engine(); } +/* + * `pmc_final` function is native implementation of equivalent events performed by + * each FSP NotifyPhase() API invocations. + * + * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits). + */ +static void pmc_final(struct device *dev) +{ + if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + pmc_clear_pmcon_sts(); +} + static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, @@ -87,6 +100,7 @@ .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, + .final = pmc_final, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = pmc_fill_ssdt, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Gerrit-Change-Number: 61649 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Add `finalize` operation for CSE
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Add `finalize` operation for CSE ...................................................................... Patch Set 24: (1 comment) File src/soc/intel/common/basecode/eop/eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/a427f5b2_5092d653 PS23, Line 20: static void do_eop_operations(void *unused) : { : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) { : /* Step 1 */ : cse_send_end_of_post(); : : /* Step 2 */ : cse_lock_config(); : : /* Step 3 */ : if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { : cse_set_to_d0i3(); : heci1_disable(); : } : } : : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) { : /* Step 4 */ : heci_set_to_d0i3(); : /* Step 5 */ : pmc_clear_pmcon_sts(); : } : } > Ack Angel, looks like we need some additional thoughts for PMC device which is not visible over bus hence, haven't selected SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config. Adding `.final` won't take any effect there. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 24 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 06 Feb 2022 12:33:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Add support for Denverton Soc
by Paul Menzel (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Felix Singer, Jeff Daly, Martin Roth, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio, Michal Motyl, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60830 ) Change subject: util/ifdtool: Add support for Denverton Soc ...................................................................... Patch Set 13: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60830/comment/eb0cce5e_cecc8d47 PS13, Line 7: Soc SOC/SoC? https://review.coreboot.org/c/coreboot/+/60830/comment/e473dce3_a0891ee7 PS13, Line 8: It’d be great, if you elaborated a little on the implementation, for example, that instead of checking the IFD version, you add new checks for EC and GBE region. Why is that necessary? -- To view, visit https://review.coreboot.org/c/coreboot/+/60830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Gerrit-Change-Number: 60830 Gerrit-PatchSet: 13 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Feb 2022 12:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `finalize` operation for CSE
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Add `finalize` operation for CSE ...................................................................... Patch Set 24: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60405/comment/e7f53531_ccfccc1a PS23, Line 26: CSE: EOP requested action: continue boot > nit: this is bit misleading in the flow? do you feel so if you read logs? I'm unable to follow you. Refer to below code https://github.com/coreboot/coreboot/blame/0eef54b8be1329e273413486f0eb764e… Kindly pick the code change if you feel something needs improvement File src/soc/intel/common/basecode/eop/Kconfig: https://review.coreboot.org/c/coreboot/+/60405/comment/454836dd_bd4bcd21 PS23, Line 9: instead > nit: instead of Ack File src/soc/intel/common/basecode/eop/eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/252cd86e_9111a08e PS23, Line 13: Sending > nit: Send Ack https://review.coreboot.org/c/coreboot/+/60405/comment/29c2b8a8_cbe371dc PS23, Line 20: static void do_eop_operations(void *unused) : { : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) { : /* Step 1 */ : cse_send_end_of_post(); : : /* Step 2 */ : cse_lock_config(); : : /* Step 3 */ : if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { : cse_set_to_d0i3(); : heci1_disable(); : } : } : : if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) { : /* Step 4 */ : heci_set_to_d0i3(); : /* Step 5 */ : pmc_clear_pmcon_sts(); : } : } > > For CSE and SPI, yes. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 24 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 06 Feb 2022 11:09:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform global reset lock
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform global reset lock ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61520/comment/2d6cbf9a_faf6e3a4 PS8, Line 7: Function > nit: Add function to perform global reset lock? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 06 Feb 2022 11:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `finalize` operation for CSE
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#24). Change subject: soc/intel/common/cse: Add `finalize` operation for CSE ...................................................................... soc/intel/common/cse: Add `finalize` operation for CSE This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects all required configs: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 24 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61519 to look at the new patch set (#7). Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function ...................................................................... soc/intel/common/cse: Add `cse_send_end_of_post()` a public function This patch creates a global function `cse_send_end_of_post()` so that IA common code may get access to this function for sending EOP command to the HECI1/CSE device. Additionally, use static variable to track and prevent sending EOP command more than once in boot flow. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc --- M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform global reset lock
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61520 to look at the new patch set (#9). Change subject: soc/intel/common/cse: Add function to perform global reset lock ...................................................................... soc/intel/common/cse: Add function to perform global reset lock This patch implements `cse_control_global_reset_lock()` as per ME BWG (doc: 627331) recommendation. It is recommended that BIOS should set this bit early on in the boot sequence, and then clear it and set the CF9LOCK bit prior to loading the OS in both an Intel CSME Enabled and a Intel CSME Disabled system. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61520/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/51nb: Convert to ASL 2.0
by HAOUAS Elyes (Code Review) 06 Feb '22

06 Feb '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61225 to look at the new patch set (#3). Change subject: mainboard/51nb: Convert to ASL 2.0 ...................................................................... mainboard/51nb: Convert to ASL 2.0 Generated 'build/dsdt.dsl' files are same. Change-Id: Iaa358bda9ec104d00e689e27a42f76a624c1be46 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/acpi/battery.asl M src/mainboard/51nb/x210/acpi/ec.asl M src/mainboard/51nb/x210/acpi/platform.asl 3 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/61225/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa358bda9ec104d00e689e27a42f76a624c1be46 Gerrit-Change-Number: 61225 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Function performs global reset lock
by Subrata Banik (Code Review) 06 Feb '22

06 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Function performs global reset lock ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/6e9db679_9a0e6a01 PS8, Line 1022: if (cse_is_hfs1_spi_protected()) > I still prefer below condition to unlock the global reset > if (cse_cse_is_hfs1_spi_protected() && !CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU) If you want me to add specific check for CSE lite then please help me to get the doc updated saying exclude the CF9LOCK for CSE lite. Also, isn't that you said, CSE update doesn't bother about global reset using PMC rather use MEI msg. Plus, it doesn't wait for so long to ensure CSE update. Marking resolved for now and please add updated doc to modify the code as requested. -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 06 Feb 2022 10:36:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2022