coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/brya: Mark the WWAN device as an UntrustedDevice
by EricR Lai (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61628 ) Change subject: mb/google/brya: Mark the WWAN device as an UntrustedDevice ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Should we put the in variant? -- To view, visit https://review.coreboot.org/c/coreboot/+/61628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e Gerrit-Change-Number: 61628 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Add support for Denverton Soc
by Angel Pons (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Felix Singer, Jeff Daly, Martin Roth, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio, Michal Motyl, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60830 ) Change subject: util/ifdtool: Add support for Denverton Soc ...................................................................... Patch Set 13: Code-Review+1 (1 comment) File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/60830/comment/f20662f1_0edd47cc PS13, Line 718: has_gbe_region = (platform != PLATFORM_DNV); : has_ec_region = (ifd_version >= IFD_VERSION_2) && (platform != PLATFORM_DNV); : has_10gbe_0_region = (platform == PLATFORM_DNV); : has_10gbe_1_region = (platform == PLATFORM_DNV); > Would it be useful to turn these into functions or macros so that they can be called from anywhere? […] These could be turned into functions, yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/60830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Gerrit-Change-Number: 60830 Gerrit-PatchSet: 13 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 11:03:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in qc_blobs[master]: sc7280/boot/shrm: Update qclib blobs binaries and release notes versi...
by Shelley Chen (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Paul Menzel, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/61590 ) Change subject: sc7280/boot/shrm: Update qclib blobs binaries and release notes version from 20 to 23 ...................................................................... Patch Set 1: (1 comment) File sc7280/shrm/Release_Notes.txt: https://review.coreboot.org/c/qc_blobs/+/61590/comment/3438c353_76bcfd47 PS1, Line 24: * dcb.bin isn't this the release notes for the shrm blob? why did you change the release notes to reference the boto blobs? -- To view, visit https://review.coreboot.org/c/qc_blobs/+/61590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: Ia53a0818e4c82301151caf86d846c98575857bc7 Gerrit-Change-Number: 61590 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 08:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: add PLATFORM_IFD2 to reduce common ifd tool change
by Subrata Banik (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Stefan Reinauer, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61576 ) Change subject: util/ifdtool: add PLATFORM_IFD2 to reduce common ifd tool change ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/61576/comment/d1c626af_9473f08c PS1, Line 227: PLATFORM_V1 > Got it. If we can differentiate IFDv2 and IFDv3 for later, I also think PLATFORM_IFD should be ok. Yup, thats the point. Thanks Will. File util/ifdtool/ifdtool.c: https://review.coreboot.org/c/coreboot/+/61576/comment/f1f5ed84_c556c3ae PS2, Line 1641: pv1 ifd2 ? You can say, *platform since Skylake are belong to IFDv2* A follow up patch can remove the for PLATFORM_SKLBKL till PLATFORM_ADL macros later. Will you be able to pick that clean up as well and make sure we have clean design between chipset prior to IFDv2 and onwards. -- To view, visit https://review.coreboot.org/c/coreboot/+/61576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22 Gerrit-Change-Number: 61576 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 08:15:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Move LAPIC configuration to MP init
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58387 ) Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init ...................................................................... cpu/x86/lapic: Move LAPIC configuration to MP init Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/cpu/qemu-x86/qemu.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c 42 files changed, 12 insertions(+), 143 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 4cf0f45..8b67a95 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -57,9 +56,6 @@ /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index d13fb9b..77f9e9a 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -8,7 +8,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -59,9 +58,6 @@ /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2915565..2ced7b9 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -57,9 +56,6 @@ /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index f84b03a..c743ffe 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <device/pci.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <smp/node.h> @@ -26,9 +25,6 @@ /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - if (CONFIG(LOGICAL_CPUS)) { siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 0f40e4b..24e3eeb 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,7 +4,6 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include "common.h" diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d4f3587..90ac5f4 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mp.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> @@ -541,9 +540,7 @@ /* Clear out pending MCEs */ configure_mca(); - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 33187d7..02e6032 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -256,9 +255,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 278d8de..4cf16d8 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -67,9 +66,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e77f9aa..35b153e 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -91,9 +91,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..52d11d7 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -7,7 +7,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> @@ -338,9 +337,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 9a17f70..15246b6 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -19,9 +18,6 @@ enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 6a2689d..d524705 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -22,9 +21,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 2344cb7..0b5d454 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index f27a63a..0e54f93 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 34646ad..bfa4a3e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -106,9 +105,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23..a481a67 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -120,9 +119,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 48a045e..f9afc6c 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> @@ -16,9 +15,6 @@ /* Update the microcode */ intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 9f365c6..294d579 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index ba3a4d6..fdc5a1e 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index ee6761e..b495dee 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -2,16 +2,12 @@ #include <device/device.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 9f01007..f0cdb58 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -2,11 +2,9 @@ #include <cpu/cpu.h> #include <device/device.h> -#include <cpu/x86/lapic.h> static void qemu_cpu_init(struct device *dev) { - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 9003534..76f2d89 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -65,13 +65,7 @@ return LAPIC_DEFAULT_BASE; } -/* See if I need to initialize the local APIC */ -static int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static void lapic_virtual_wire_mode_init(void) +void setup_lapic_interrupts(void) { /* * Set Task Priority to 'accept all'. @@ -94,17 +88,3 @@ lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } - -void setup_lapic(void) -{ - /* Enable the local APIC */ - if (need_lapic_init()) - enable_lapic(); - else if (!CONFIG(UDELAY_LAPIC)) - disable_lapic(); - - /* This programming is for PIC mode i8259 interrupts to be delivered to CPU - while LAPIC is enabled. */ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); -} diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be2..837d32f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -298,6 +298,11 @@ cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); #endif + + /* Ensure the local APIC is enabled */ + enable_lapic(); + setup_lapic_interrupts(); + cpu_initialize(index); spin_unlock(&start_cpu_lock); @@ -376,8 +381,10 @@ info = cpu_info(); /* Ensure the local APIC is enabled */ - if (is_smp_boot()) + if (is_smp_boot()) { enable_lapic(); + setup_lapic_interrupts(); + } /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index abe903c..fee5940 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -185,6 +185,7 @@ /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); info->cpu = cpus_dev[info->index]; @@ -543,6 +544,7 @@ /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); /* Set the device path of the boot CPU. */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e131d2e..7006dbc 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -177,6 +177,6 @@ void enable_lapic(void); void disable_lapic(void); -void setup_lapic(void); +void setup_lapic_interrupts(void); #endif /* CPU_X86_LAPIC_H */ diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 440b5ba..adc99d0 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -62,7 +61,6 @@ static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b80b0f7..de6e9c0 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,7 +10,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -66,7 +65,6 @@ static void model_17_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 0aa487c..c355a70 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -10,7 +10,6 @@ #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -64,7 +63,6 @@ static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6be76bf..3cd3a95 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -65,7 +64,6 @@ static void model_15_init(struct device *dev) { check_mca(); - setup_lapic(); /* * Per AMD, sync an undocumented MSR with the PSP base address. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 3b3a7a2..426f621 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -110,9 +109,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 74aeee9..e892017 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -5,7 +5,6 @@ #include <console/console.h> #include "chip.h" #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> @@ -154,8 +153,6 @@ x86_setup_mtrrs_with_detect(); x86_mtrr_check(); - /* Enable the local CPU apics */ - setup_lapic(); } #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index eb24f7b..1dbc3d7 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -36,9 +36,6 @@ { printk(BIOS_DEBUG, "Init BayTrail core.\n"); - /* Enable the local CPU apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7c7a15d..b11007d 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,9 +36,6 @@ { printk(BIOS_DEBUG, "Init Braswell core.\n"); - /* Enable the local cpu apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 10921a2..b7ca2b4 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -118,9 +117,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(cfg); diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 3747a48..93657fe 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -100,9 +100,6 @@ /* Enable Turbo */ enable_turbo(); - /* Enable the local CPU apics */ - setup_lapic(); - /* Enable speed step. Always ON.*/ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0cc3935..3e0dae1 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -3,7 +3,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> #include <cpu/intel/common/common.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <device/pci.h> @@ -70,9 +69,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 37978ea..f503fcd 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -103,9 +102,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index af39c94..01cd6ac 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -70,9 +69,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63a0466..3439836 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> @@ -118,9 +117,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d225c50..ffccdcc 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -7,7 +7,6 @@ */ #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -76,9 +75,7 @@ * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index a4da344..41dde0d 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -3,7 +3,6 @@ #include <arch/ioapic.h> #include <console/console.h> #include <console/debug.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -181,7 +180,6 @@ override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); - setup_lapic(); p2sb_unhide(); } diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 07c2db7..0951ae3 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -11,7 +11,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <intelblocks/cpulib.h> @@ -78,7 +77,6 @@ printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); - setup_lapic(); /* * Set HWP base feature, EPP reg enumeration, lock thermal and msr -- To view, visit https://review.coreboot.org/c/coreboot/+/58387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Gerrit-Change-Number: 58387 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55413 ) Change subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER ...................................................................... cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c 7 files changed, 0 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 3e4de1f..33187d7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -12,18 +12,6 @@ #include "chip.h" -static void init_timer(void) -{ - /* Set the APIC timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) @@ -271,9 +259,6 @@ /* Enable the local CPU APICs */ setup_lapic(); - /* Initialize the APIC timer */ - init_timer(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a..744c92b 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/lapic.h> #include <arch/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> @@ -42,8 +41,6 @@ /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - enable_lapic(); - /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c79..4980f9b 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <device/mmio.h> #include <elog.h> -#include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <security/intel/txt/txt.h> #include <security/intel/txt/txt_register.h> @@ -20,8 +19,6 @@ /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - enable_lapic(); - early_pch_init(); /* Perform some early chipset initialization required diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d6..0a61780 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <cf9_reset.h> -#include <cpu/x86/lapic.h> #include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -30,8 +29,6 @@ int s3resume = 0; u8 spd_map[4] = {}; - enable_lapic(); - mainboard_lpc_decode(); if (mchbar_read16(SSKPD) == 0xcafe) { diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..242100b 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/pci_ops.h> -#include <cpu/x86/lapic.h> #include <timestamp.h> #include <romstage_handoff.h> #include "ironlake.h" @@ -27,8 +26,6 @@ int s3resume = 0; u8 spd_addrmap[4] = {}; - enable_lapic(); - /* TODO, make this configurable */ ironlake_early_initialization(IRONLAKE_MOBILE); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420c..a98ae99 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -9,7 +9,6 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> -#include <cpu/x86/lapic.h> #include "raminit.h" #include "pineview.h" @@ -31,8 +30,6 @@ int boot_path, cbmem_was_initted; int s3resume = 0; - enable_lapic(); - /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); pineview_early_init(); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 71b8e12..a6f626a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/pci_ops.h> -#include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include "sandybridge.h" #include <arch/romstage.h> @@ -54,8 +53,6 @@ if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset(); - enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/55413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Gerrit-Change-Number: 55413 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55413 ) Change subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER ...................................................................... Patch Set 9: (2 comments) File src/cpu/intel/model_1067x/model_1067x_init.c: https://review.coreboot.org/c/coreboot/+/55413/comment/8ead0e55_59db0a27 PS1, Line 18: lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); > For Intel CPUs, only model_1067x enters payload with LAPIC timer initialised. […] Ack File src/northbridge/intel/gm45/romstage.c: https://review.coreboot.org/c/coreboot/+/55413/comment/ac7f1611_7272a289 PS1, Line 45: enable_lapic(); > I'd explain in the commit message why these `enable_lapic()` calls are dropped. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Gerrit-Change-Number: 55413 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Feb 2022 07:52:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Fix choice X2APIC_ONLY
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60213 ) Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY ...................................................................... cpu/x86/lapic: Fix choice X2APIC_ONLY When sending self an IPI, some instructions may be processed before IPI is serviced. Spend some time doing nothing, to avoid entering a printk() and acquiring console_lock and dead-locking. Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/lapic.h 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index c1603f2..e131d2e 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -145,8 +145,16 @@ static __always_inline void lapic_send_ipi_self(uint32_t icrlow) { + int i = 1000; + /* LAPIC_DEST_SELF does not support all delivery mode -fields. */ lapic_send_ipi(icrlow, lapicid()); + + /* In case of X2APIC force a short delay, to prevent deadlock in a case + * the immediately following code acquires some lock, like with printk(). + */ + while (CONFIG(X2APIC_ONLY) && i--) + cpu_relax(); } static __always_inline void lapic_send_ipi_others(uint32_t icrlow) -- To view, visit https://review.coreboot.org/c/coreboot/+/60213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb Gerrit-Change-Number: 60213 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/lapic: Add lapic_send_ipi_self,others()
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60713 ) Change subject: cpu/x86/lapic: Add lapic_send_ipi_self,others() ...................................................................... cpu/x86/lapic: Add lapic_send_ipi_self,others() This avoids unnecessary passing of APIC ID parameter and allows some minor optimisation for X2APIC mode. Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60713 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/lapic/lapic_cpu_stop.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h 3 files changed, 16 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c index e933ce4..1affe15 100644 --- a/src/cpu/x86/lapic/lapic_cpu_stop.c +++ b/src/cpu/x86/lapic/lapic_cpu_stop.c @@ -55,7 +55,7 @@ printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); mdelay(10); @@ -63,7 +63,7 @@ dprintk(BIOS_SPEW, "Deasserting INIT.\n"); /* Deassert the LAPIC INIT */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); halt(); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index e1979c8..abe903c 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -423,8 +423,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, - 0); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "timed out.\n"); @@ -464,7 +463,7 @@ } /* Send INIT IPI to all but self. */ - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT); if (!CONFIG(X86_INIT_NEED_1_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); @@ -649,7 +648,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); + lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI); if (lapic_busy()) { if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) { diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 779799e..c1603f2 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -143,6 +143,17 @@ return lapicid; } +static __always_inline void lapic_send_ipi_self(uint32_t icrlow) +{ + /* LAPIC_DEST_SELF does not support all delivery mode -fields. */ + lapic_send_ipi(icrlow, lapicid()); +} + +static __always_inline void lapic_send_ipi_others(uint32_t icrlow) +{ + lapic_send_ipi(LAPIC_DEST_ALLBUT | icrlow, 0); +} + #if !CONFIG(AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_stop.c -- To view, visit https://review.coreboot.org/c/coreboot/+/60713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Gerrit-Change-Number: 60713 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/lapic: Unify some parameter
by Kyösti Mälkki (Code Review) 05 Feb '22

05 Feb '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60712 ) Change subject: cpu/x86/lapic: Unify some parameter ...................................................................... cpu/x86/lapic: Unify some parameter Change-Id: I790fddea747f5db0536159e6c2ac90ea1da2830e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60712 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/lapic.h 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index af0793b..779799e 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -18,9 +18,9 @@ write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); } -static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) +static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t icrhi) { - xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + xapic_write(LAPIC_ICR2, icrhi); xapic_write(LAPIC_ICR, icrlow); } @@ -51,10 +51,10 @@ wrmsr(index, msr); } -static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) +static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t icrhi) { msr_t icr; - icr.hi = apicid; + icr.hi = icrhi; icr.lo = icrlow; wrmsr(X2APIC_MSR_ICR_ADDRESS, icr); } @@ -112,7 +112,7 @@ if (is_x2apic_mode()) x2apic_send_ipi(icrlow, apicid); else - xapic_send_ipi(icrlow, apicid); + xapic_send_ipi(icrlow, SET_LAPIC_DEST_FIELD(apicid)); } static __always_inline int lapic_busy(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/60712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790fddea747f5db0536159e6c2ac90ea1da2830e Gerrit-Change-Number: 60712 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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