coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/alderlake: Update USB2_PORT_MAX macro
by Angel Pons (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61623 ) Change subject: soc/intel/alderlake: Update USB2_PORT_MAX macro ...................................................................... Patch Set 1: (1 comment) Commit Message: PS1: Why not add a new macro? -- To view, visit https://review.coreboot.org/c/coreboot/+/61623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464f139d8e367907191c04f9170ac53d327776ee Gerrit-Change-Number: 61623 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 20:24:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec: Get rid of unnecessary blank line {before,after} brace
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61556 ) Change subject: src/ec: Get rid of unnecessary blank line {before,after} brace ...................................................................... src/ec: Get rid of unnecessary blank line {before,after} brace Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/ec.c M src/ec/lenovo/h8/chip.h M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c 5 files changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index eb0b5ff..6389383 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -113,7 +113,6 @@ printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); pc_keyboard_init(NO_AUX_DEVICE); - } static struct device_operations ops = { diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 642c313..e9a0939 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1775,7 +1775,6 @@ int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) { - struct ec_params_regulator_is_enabled params = { .index = index, }; diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index d1aa9fe..440c2fc 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -4,7 +4,6 @@ #define EC_LENOVO_H8EC_CHIP_H struct ec_lenovo_h8_config { - u8 config0; u8 config1; u8 config2; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index b081ec8..bbe6490 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -18,7 +18,6 @@ { ec_write(H8_TRACKPOINT_CTRL, on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); - } /* Controls radio-off pin in WLAN MiniPCIe slot. */ @@ -119,7 +118,6 @@ return; ec_clr_bit(0x10 + (event >> 3), event & 7); - } void h8_usb_always_on_enable(enum usb_always_on on) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index ebcbcde..c232a51 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -25,7 +25,6 @@ pmh7_register_set_bit(0x60, 3); else pmh7_register_clear_bit(0x60, 3); - } void pmh7_touchpad_enable(int onoff) -- To view, visit https://review.coreboot.org/c/coreboot/+/61556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed Gerrit-Change-Number: 61556 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable UntrustedDevice wifi property for brask & brya
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61385 ) Change subject: mb/google/brya: Enable UntrustedDevice wifi property for brask & brya ...................................................................... mb/google/brya: Enable UntrustedDevice wifi property for brask & brya The CNVi Wifi controller is considered an untrusted device for ChromeOS, therefore enable the new UntrustedDevice property for the cnvi_wifi device on all brya & brask boards. BUG=b:215424986 TEST=dump SSDT on google/redrix, verify it contains the expected UntrustedDevice property Change-Id: Ieff6eea0865125a7c0f626e1981dda1c9532ebb1 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61385 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 466f08a..ec6fd96 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -117,6 +117,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "is_untrusted" = "true" device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index ee0fbce..7cc0204 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -143,6 +143,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "is_untrusted" = "true" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/61385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieff6eea0865125a7c0f626e1981dda1c9532ebb1 Gerrit-Change-Number: 61385 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/wifi/generic: Add support for UntrustedDevice ACPI property
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61384 ) Change subject: drivers/wifi/generic: Add support for UntrustedDevice ACPI property ...................................................................... drivers/wifi/generic: Add support for UntrustedDevice ACPI property The Linux kernel has the idea of an "untrusted" PCI device, which may have limited I/O and memory access permissions, depending on which IOMMU domains it may be a part of. https://crrev.com/c/3406512 is a backport to the ChromiumOS kernel which checks for this property. BUG=b:215424986 TEST=dump SSDT on google/redrix, verify it contains the expected UntrustedDevice property Change-Id: I1a02ca7c5f717097ec97cf6373b9e0b81a13e05d Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61384 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 3cc1c63..f4ffa5e 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -26,6 +26,9 @@ /* Unique ID for the WIFI _DSM */ #define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" +/* Unique ID for the Wifi _DSD */ +#define ACPI_DSD_UNTRUSTED_UUID "88566a92-1a61-466d-949a-6d12809d480c" + __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { return -1; @@ -508,10 +511,22 @@ /* Scope */ acpigen_write_scope(scope); - /* Wake capabilities */ - if (config) + if (config) { + /* Wake capabilities */ acpigen_write_PRW(config->wake, ACPI_S3); + /* Add _DSD for UntrustedDevice property. */ + if (config->is_untrusted) { + struct acpi_dp *dsd, *pkg; + + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(ACPI_DSD_UNTRUSTED_UUID); + acpi_dp_add_integer(pkg, "UntrustedDevice", 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + } + } + /* Fill regulatory domain structure */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) { /* diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index e3b0ba5..35726f2 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -9,6 +9,9 @@ */ struct drivers_wifi_generic_config { unsigned int wake; + /* When set to true, this will add a _DSD which contains a single + property, `UntrustedDevice`, set to 1, to the ACPI Device. */ + bool is_untrusted; }; #endif /* _GENERIC_WIFI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a02ca7c5f717097ec97cf6373b9e0b81a13e05d Gerrit-Change-Number: 61384 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/ifdtool: Add additional regions for platforms that support them
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60829 ) Change subject: util/ifdtool: Add additional regions for platforms that support them ...................................................................... util/ifdtool: Add additional regions for platforms that support them Some Intel SoCs such as Denverton support additional SPI regions for things like Innovation Engine firmware or 10GbE LAN firmwares Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 34 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ca5d3b8..586f50f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -40,10 +40,17 @@ { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, - { "Reserved", "res1", "flashregion_5_reserved.bin", NULL }, - { "Reserved", "res2", "flashregion_6_reserved.bin", NULL }, - { "Reserved", "res3", "flashregion_7_reserved.bin", NULL }, + { "Device Exp1", "devexp", "flashregion_5_device_exp.bin", "SI_DEVICEEXT" }, + { "Secondary BIOS", "bios2", "flashregion_6_bios2.bin", "SI_BIOS2" }, + { "Reserved", "res7", "flashregion_7_reserved.bin", NULL }, { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, + { "Device Exp2", "devexp2", "flashregion_9_device_exp.bin", "SI_DEVICEEXT2" }, + { "IE", "ie", "flashregion_10_ie.bin", "SI_IE" }, + { "10GbE_0", "10gbe_0", "flashregion_11_10gbe0.bin", "SI_10GBE0" }, + { "10GbE_1", "10gbe_1", "flashregion_12_10gbe1.bin", "SI_10GBE1" }, + { "Reserved", "res13", "flashregion_13_reserved.bin", NULL }, + { "Reserved", "res14", "flashregion_14_reserved.bin", NULL }, + { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT" }, }; /* port from flashrom */ @@ -1642,7 +1649,8 @@ " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - "<region> is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " + "Device Exp1, EC, Device Exp2, IE, 10GbE_0, 10GbE_1, PTT\n" "\n"); } @@ -1731,16 +1739,26 @@ region_type = 2; else if (!strcasecmp("GbE", region_type_string)) region_type = 3; - else if (!strcasecmp("Platform", region_type_string)) + else if (!strcasecmp("Platform Data", region_type_string)) region_type = 4; - else if (!strcasecmp("res1", region_type_string)) + else if (!strcasecmp("Device Exp1", region_type_string)) region_type = 5; - else if (!strcasecmp("res2", region_type_string)) + else if (!strcasecmp("Secondary BIOS", region_type_string)) region_type = 6; - else if (!strcasecmp("res3", region_type_string)) + else if (!strcasecmp("Reserved", region_type_string)) region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; + else if (!strcasecmp("Device Exp2", region_type_string)) + region_type = 9; + else if (!strcasecmp("IE", region_type_string)) + region_type = 10; + else if (!strcasecmp("10GbE_0", region_type_string)) + region_type = 11; + else if (!strcasecmp("10GbE_1", region_type_string)) + region_type = 12; + else if (!strcasecmp("PTT", region_type_string)) + region_type = 15; if (region_type == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 4f63e20..bde104a 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -117,7 +117,7 @@ } __attribute__((packed)) fdbar_t; // regions -#define MAX_REGIONS 9 +#define MAX_REGIONS 16 #define MAX_REGIONS_OLD 5 enum flash_regions { @@ -126,7 +126,14 @@ REGION_ME, REGION_GBE, REGION_PDR, + REGION_DEV_EXP1, + REGION_BIOS2, REGION_EC = 8, + REGION_DEV_EXP2, + REGION_IE, + REGION_10GB_0, + REGION_10GB_1, + REGION_PTT = 15, }; typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/60829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5 Gerrit-Change-Number: 60829 Gerrit-PatchSet: 13 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Report SMBIOS memory speed in MT/s
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61504 ) Change subject: nb/intel/haswell: Report SMBIOS memory speed in MT/s ...................................................................... nb/intel/haswell: Report SMBIOS memory speed in MT/s The memory speed values in SMBIOS tables are expressed in MT/s, not MHz. Adjust the reported frequency values accordingly. Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61504 Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/haswell/haswell_mrc/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e46eb57..fedb683 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -234,7 +234,7 @@ memset(mem_info, 0, sizeof(struct memory_info)); - const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; + const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < NUM_CHANNELS; ch++) { const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); @@ -246,7 +246,7 @@ dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_frequency; + dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); dimm->channel_num = ch; dimm->dimm_num = d_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/61504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Gerrit-Change-Number: 61504 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61601 ) Change subject: soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA ...................................................................... soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/chausie/mainboard.c M src/soc/amd/sabrina/fch.c M src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h 3 files changed, 1 insertion(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index d667f5a..073c168 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -48,7 +48,6 @@ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, { PIRQ_GPIO, 7, 7 }, { PIRQ_I2C2, PIRQ_NC, PIRQ_NC }, diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c index 69149f0..9be7dd8 100644 --- a/src/soc/amd/sabrina/fch.c +++ b/src/soc/amd/sabrina/fch.c @@ -52,7 +52,6 @@ { PIRQ_GPIOA, "GPIOa" }, { PIRQ_GPIOB, "GPIOb" }, { PIRQ_GPIOC, "GPIOc" }, - { PIRQ_SATA, "SATA" }, { PIRQ_EMMC, "eMMC" }, { PIRQ_GPP0, "GPP0" }, { PIRQ_GPP1, "GPP1" }, diff --git a/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h index a3f8b82..424b224 100644 --- a/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #ifndef AMD_SABRINA_AMD_PCI_INT_DEFS_H #define AMD_SABRINA_AMD_PCI_INT_DEFS_H @@ -40,9 +38,7 @@ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x40 reserved */ -#define PIRQ_SATA 0x41 /* SATA */ -/* 0x42 reserved */ +/* 0x24-0x42 reserved */ #define PIRQ_EMMC 0x43 /* eMMC */ /* 0x44-0x4f reserved */ #define PIRQ_GPP0 0x50 /* GPPInt0 */ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Gerrit-Change-Number: 61601 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODO
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61600 ) Change subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODO ...................................................................... soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODO The common AMD data fabric register access code is valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I97fb2c6006c09297584845a83342e75058d35713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 5044f8d..b0804c7 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -48,7 +48,7 @@ select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97fb2c6006c09297584845a83342e75058d35713 Gerrit-Change-Number: 61600 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMU
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61599 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMU ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMU The common AMD SMU code and the common AMD SMN access code that gets selected by the common SMU code are valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index c2b9733..5044f8d 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -67,7 +67,7 @@ select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa Gerrit-Change-Number: 61599 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOAC
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61598 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOAC ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOAC The common AMD FCH AOAC bit definitions and helper functions are correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 2c54f61..c2b9733 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -45,7 +45,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f Gerrit-Change-Number: 61598 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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