coreboot-gerrit February 2022

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Change in coreboot[master]: mb/google/brya: Mark the WWAN device as an UntrustedDevice
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61628 ) Change subject: mb/google/brya: Mark the WWAN device as an UntrustedDevice ...................................................................... mb/google/brya: Mark the WWAN device as an UntrustedDevice The ChromiumOS kernel has the ability to restrict devices to their own IOMMU security domains when ACPI passes this property to a device downstream of a PCIe RP. BUG=b:215424986 TEST=verified the property is found and WWAN is restricted to its own IOMMU domain as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/61628/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c0b8a34..14a34ab 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -14,6 +14,7 @@ select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_PCIE_GENERIC select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index ee0fbce..060f1fd 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -161,6 +161,10 @@ .clk_req = 5, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip drivers/pcie/generic + register "is_untrusted" = "1" + device pci 0 on end + end end #PCIE6 WWAN device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e Gerrit-Change-Number: 61628 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pcie/generic: Add new pcie generic chip driver
by Tim Wawrzynczak (Code Review) 04 Feb '22

04 Feb '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61627 ) Change subject: drivers/pcie/generic: Add new pcie generic chip driver ...................................................................... drivers/pcie/generic: Add new pcie generic chip driver This new chip driver will be used for attaching ACPI properties to PCIe endpoints. The first property it supports is "UntrustedDevice." This property can be used by a payload to, e.g., restrict the device to its own IOMMU domain for security purposes. The new property is added by adding a _DSD and an integer property set to 1. Example of the property from google/brya0: Scope (\_SB.PCI0.RP01) { Device (DEV0) { Name (_ADR, 0x0000000000000000) // _ADR: Address Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } } BUG=b:215424986 TEST=boot patch train on google/brya0, dump SSDT, see above for snippet Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf --- A src/drivers/pcie/generic/Kconfig A src/drivers/pcie/generic/Makefile.inc A src/drivers/pcie/generic/chip.h A src/drivers/pcie/generic/generic.c 4 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/61627/1 diff --git a/src/drivers/pcie/generic/Kconfig b/src/drivers/pcie/generic/Kconfig new file mode 100644 index 0000000..f3a8441 --- /dev/null +++ b/src/drivers/pcie/generic/Kconfig @@ -0,0 +1,11 @@ +config DRIVERS_PCIE_GENERIC + bool + default n + depends on HAVE_ACPI_TABLES + help + This driver allows attaching arbitrary ACPI properties to + arbitrary PCI root ports or devices. Currently it supports one + property, "UntrustedDevice" which can be used by indicate to + the operating system that this device may be considered + untrusted, and appropriate policies, e.g. IO/MMU isolation, + should take place. diff --git a/src/drivers/pcie/generic/Makefile.inc b/src/drivers/pcie/generic/Makefile.inc new file mode 100644 index 0000000..f634f25 --- /dev/null +++ b/src/drivers/pcie/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_PCIE_GENERIC) += generic.c diff --git a/src/drivers/pcie/generic/chip.h b/src/drivers/pcie/generic/chip.h new file mode 100644 index 0000000..f122a55 --- /dev/null +++ b/src/drivers/pcie/generic/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _PCIE_GENERIC_H_ +#define _PCIE_GENERIC_H_ + +struct drivers_pcie_generic_config { + bool is_untrusted; +}; + +#endif /* _PCIE_GENERIC_H_ */ diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c new file mode 100644 index 0000000..275fd3c --- /dev/null +++ b/src/drivers/pcie/generic/generic.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <device/device.h> +#include <device/pci.h> +#include "chip.h" + +static const char *pcie_generic_acpi_name(const struct device *dev) +{ + return "DEV0"; +} + +static void pcie_generic_fill_ssdt(const struct device *dev) +{ + struct drivers_pcie_generic_config *config = dev->chip_info; + struct acpi_dp *dsd; + + if (!config || !dev || !dev->bus || !dev->bus->dev) + return; + + if (!config->is_untrusted) + return; + + const char *scope = acpi_device_path(dev->bus->dev); + const char *name = acpi_device_name(dev); + + acpigen_write_scope(scope); + acpigen_write_device(name); + acpigen_write_ADR_pci_device(dev); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "UntrustedDevice", 1); + acpi_dp_write(dsd); + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + printk(BIOS_INFO, "%s.%s: Enable ACPI properties for %s (%s)\n", scope, name, + dev_path(dev), dev->chip_ops->name); +} + +struct device_operations pcie_generic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_name = pcie_generic_acpi_name, + .acpi_fill_ssdt = pcie_generic_fill_ssdt, +}; + +static void pcie_generic_enable(struct device *dev) +{ + dev->ops = &pcie_generic_ops; +} + +struct chip_operations drivers_pcie_generic_ops = { + CHIP_NAME("PCIe Device") + .enable_dev = pcie_generic_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/61627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf Gerrit-Change-Number: 61627 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/3d3af57f_ca10df39 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) > If platforms have integrated with Consumer SKU, BIOS should allow CSE Region to be updated if HFSTS1 […] Sorry, didn't get your point. -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Subrata Banik (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/54e95dfa_5a41a5bc PS5, Line 1014: /* > This is not applicable if CSE Lite is integrated instead CSE Consumer SKU since Chrome platform uses HMRFPO mechanism to update the CSE Region (specifically CSE RW). So, please add below code the function. Please not Chrome platform doesn't use FPT tool to update the CSE region. > > if (CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) > return; Sure, if this is the requirement for Chrome OS then I have below opens: 1. Please update the ME BWG to document the expectation for applicable CSE LITE SKU. 2. Please raise a bug for FSP, as today in ADL FSP does below highlighted programming as well unconditionally (please investigate inside FSP Notify API code) without any flag about LITE or consumer, wondering how so far on TGL, JSL and ADL CSE FW update works with below implementation inside FSP. Do you want me to raise those 2 bugs ? "BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) prior to transferring control to the OS." -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:36:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61626 ) Change subject: soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO ...................................................................... soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO Sabrina is compatible with the common AMD ACPIMMIO function block mapping and access functions. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/61626/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index b0804c7..9e17e27 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -41,7 +41,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Gerrit-Change-Number: 61626 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61625 ) Change subject: soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions ...................................................................... soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions The PM2 ACPIMMIO region should only be accessed with 8 bit accesses. Using 16 or 32 bit read accesses will return the data from the first byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in only the first byte being written which is both unexpected behavior. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/61625/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ae86730..2d632f6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -198,31 +198,11 @@ return read8(acpimmio_pmio2 + reg); } -static inline uint16_t pm2_read16(uint8_t reg) -{ - return read16(acpimmio_pmio2 + reg); -} - -static inline uint32_t pm2_read32(uint8_t reg) -{ - return read32(acpimmio_pmio2 + reg); -} - static inline void pm2_write8(uint8_t reg, uint8_t value) { write8(acpimmio_pmio2 + reg, value); } -static inline void pm2_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_pmio2 + reg, value); -} - -static inline void pm2_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_pmio2 + reg, value); -} - static inline uint8_t acpi_read8(uint8_t reg) { return read8(acpimmio_acpi + reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/61625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Gerrit-Change-Number: 61625 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61624 ) Change subject: soc/amd/common/block/acpimmio/print_reset_status: extend bit name table ...................................................................... soc/amd/common/block/acpimmio/print_reset_status: extend bit name table Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 --- M src/soc/amd/common/block/acpimmio/print_reset_status.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/61624/1 diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c index 309401e..5ff0412 100644 --- a/src/soc/amd/common/block/acpimmio/print_reset_status.c +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -41,13 +41,15 @@ [20] = "DoFullReset", [21] = "SleepReset", [22] = "KbReset", - [23] = "LtReset", + [23] = "LtReset/ShutdownMsg", [24] = "FailBootRst", [25] = "WatchdogIssueReset", [26] = "RemoteResetFromASF", [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", + [30] = "SdpParityErr", + [31] = "SwSyncFloodFlag", }; printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); -- To view, visit https://review.coreboot.org/c/coreboot/+/61624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Gerrit-Change-Number: 61624 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Pass log_state to vtxprintf()
by Felix Held (Code Review) 04 Feb '22

04 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61580 ) Change subject: console: Pass log_state to vtxprintf() ...................................................................... console: Pass log_state to vtxprintf() This patch makes a slight change in the way CONSOLE_LOG_FAST and CONSOLE_LOG_ALL are differentiated, by no longer passing a different tx_byte() function pointer and instead using the `data` argument to vtxprintf() to encode the difference. It also passes the message log level through to the tx_byte() function this way, which will be needed in the next patch. Change-Id: I0bba134cd3e70c2032689abac83ff53d7cdf2d7f Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61580 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/console/printk.c 1 file changed, 19 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/console/printk.c b/src/console/printk.c index 1ed39cb..ef3d29f 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -59,37 +59,43 @@ console_time_stop(); } +union log_state { + void *as_ptr; + struct { + uint8_t level; + uint8_t speed; + }; +}; + static void wrap_putchar(unsigned char byte, void *data) { - console_tx_byte(byte); -} + union log_state state = { .as_ptr = data }; -static void wrap_putchar_cbmemc(unsigned char byte, void *data) -{ - __cbmemc_tx_byte(byte); + if (state.speed == CONSOLE_LOG_FAST) + __cbmemc_tx_byte(byte); + else + console_tx_byte(byte); } int vprintk(int msg_level, const char *fmt, va_list args) { - int i, log_this; + union log_state state = { .level = msg_level }; + int i; if (CONFIG(SQUELCH_EARLY_SMP) && ENV_ROMSTAGE_OR_BEFORE && !boot_cpu()) return 0; - log_this = console_log_level(msg_level); - if (log_this < CONSOLE_LOG_FAST) + state.speed = console_log_level(msg_level); + if (state.speed < CONSOLE_LOG_FAST) return 0; spin_lock(&console_lock); console_time_run(); - if (log_this == CONSOLE_LOG_FAST) { - i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL); - } else { - i = vtxprintf(wrap_putchar, fmt, args, NULL); + i = vtxprintf(wrap_putchar, fmt, args, state.as_ptr); + if (state.speed != CONSOLE_LOG_FAST) console_tx_flush(); - } console_time_stop(); -- To view, visit https://review.coreboot.org/c/coreboot/+/61580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bba134cd3e70c2032689abac83ff53d7cdf2d7f Gerrit-Change-Number: 61580 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/de458052_e61efff0 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) If platforms have integrated with Consumer SKU, BIOS should allow CSE Region to be updated if HFSTS1 [4] is set. The pre-requisites are not necessary here. -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:24:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Sridhar Siricilla (Code Review) 04 Feb '22

04 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 ) Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61520/comment/8562a6e1_d27d98bc PS5, Line 9: perform the required CSE : lock configuration nit: controls the global reset lock configuration File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/61520/comment/639ff94c_b554a81d PS5, Line 1012: cse_lock_config nit: cse_control_global_reset_lock? https://review.coreboot.org/c/coreboot/+/61520/comment/b7634320_905e390b PS5, Line 1014: /* This is not applicable if CSE Lite is integrated instead CSE Consumer SKU since Chrome platform uses HMRFPO mechanism to update the CSE Region (specifically CSE RW). So, please add below code the function. Please not Chrome platform doesn't use FPT tool to update the CSE region. if (CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Feb 2022 16:14:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2022