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Hello build bot (Jenkins), Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID
......................................................................
src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID
Add new IGD Id.
Reference: EDS Vol 1 (640228)
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com>
Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/meteorlake/bootblock/report_platform.c
3 files changed, 20 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/68305/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 )
Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
......................................................................
Patch Set 16:
(1 comment)
File src/soc/amd/common/acpi/dptc.asl:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161824):
https://review.coreboot.org/c/coreboot/+/68471/comment/12631631_ff41e065
PS16, Line 67: }
trailing whitespace
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 )
Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66579/comment/861bb359_727c2a39
PS4, Line 15: get_me_fw_version
I didn't get you, get_me_fw_version() shouldn't be the last HECI command from coreboot to CSE in the boot flow. Issue is not seen after sending EOP command to CSE?
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Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Any change by the index? What for?
Typically, when you have more resources under same device like host bring aka 0:0:0 device, then it make sense to add more than incremental index. Other wise always the index started with 0th base.
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Change subject: soc/intel/meteorlake: Fix incompatible function pointers
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/66263/comment/431c0a84_5c011f44
PS2, Line 442:
> please remove the extra space
Done
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Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68954/comment/d061e623_07d95a51
PS1, Line 11:
> Could you also mention that in this CL?
Done in the TEST message.
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Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68954
to look at the new patch set (#4).
Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
soc/amd/mendocino: Enable x86 SHA accelerator
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.
Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/mendocino/Kconfig
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/68954/4
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