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Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
......................................................................
Patch Set 16:
(1 comment)
File src/soc/amd/common/acpi/dptc.asl:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161824):
https://review.coreboot.org/c/coreboot/+/68471/comment/12631631_ff41e065
PS16, Line 67: }
trailing whitespace
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Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66579/comment/861bb359_727c2a39
PS4, Line 15: get_me_fw_version
I didn't get you, get_me_fw_version() shouldn't be the last HECI command from coreboot to CSE in the boot flow. Issue is not seen after sending EOP command to CSE?
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Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Any change by the index? What for?
Typically, when you have more resources under same device like host bring aka 0:0:0 device, then it make sense to add more than incremental index. Other wise always the index started with 0th base.
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Change subject: soc/intel/meteorlake: Fix incompatible function pointers
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/66263/comment/431c0a84_5c011f44
PS2, Line 442:
> please remove the extra space
Done
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Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68954/comment/d061e623_07d95a51
PS1, Line 11:
> Could you also mention that in this CL?
Done in the TEST message.
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Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68954
to look at the new patch set (#4).
Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
soc/amd/mendocino: Enable x86 SHA accelerator
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.
Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/mendocino/Kconfig
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/68954/4
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Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
Patch Set 3:
(2 comments)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/d5a63f49_a52899cc
PS2, Line 26: ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
> Build error from Jenkins: […]
Ack. That was a bad mistake from my side. Sorry about that and Thanks for catching it.
https://review.coreboot.org/c/coreboot/+/68953/comment/4b8332d5_92d0c6de
PS2, Line 43: X86_SHA_EXT="$$(X86_SHA_EXT_$(1))" \
> I think a more generic way to write this could be […]
Done
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Hello build bot (Jenkins), Raul Rangel, Kangheui Won, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
security/vboot: Update build rules using x86 SHA extension
Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.
Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/security/vboot/Makefile.inc
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/68953/3
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Change subject: /: Update and rewrite README.md
......................................................................
Patch Set 4: Code-Review+2
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