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Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
Patch Set 3:
(2 comments)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/d5a63f49_a52899cc
PS2, Line 26: ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
> Build error from Jenkins: […]
Ack. That was a bad mistake from my side. Sorry about that and Thanks for catching it.
https://review.coreboot.org/c/coreboot/+/68953/comment/4b8332d5_92d0c6de
PS2, Line 43: X86_SHA_EXT="$$(X86_SHA_EXT_$(1))" \
> I think a more generic way to write this could be […]
Done
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Hello build bot (Jenkins), Raul Rangel, Kangheui Won, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68953
to look at the new patch set (#3).
Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
security/vboot: Update build rules using x86 SHA extension
Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.
Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/security/vboot/Makefile.inc
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/68953/3
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Change subject: /: Update and rewrite README.md
......................................................................
Patch Set 4: Code-Review+2
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69052 )
Change subject: mb/google/brya: Create marasov variant
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/brya: Create marasov variant
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Change subject: mb/google/brya: Create marasov variant
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161819):
https://review.coreboot.org/c/coreboot/+/69052/comment/6c2fd3bb_6040dbad
PS1, Line 9: # See util/spd_tools/README.md for more details and instructions.
'README' may be misspelled - perhaps 'README'?
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Change subject: mb/google/brya: Create marasov variant
......................................................................
mb/google/brya: Create marasov variant
Create the marasov variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:254365935
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MARASOV
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/marasov/include/variant/ec.h
A src/mainboard/google/brya/variants/marasov/include/variant/gpio.h
A src/mainboard/google/brya/variants/marasov/memory/Makefile.inc
A src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/marasov/overridetree.cb
7 files changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/69052/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index f54e96b..68c2780 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -218,6 +218,7 @@
default "Lisbon" if BOARD_GOOGLE_LISBON
default "Zydron" if BOARD_GOOGLE_ZYDRON
default "Gladios" if BOARD_GOOGLE_GLADIOS
+ default "Marasov" if BOARD_GOOGLE_MARASOV
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -258,6 +259,7 @@
default "lisbon" if BOARD_GOOGLE_LISBON
default "zydron" if BOARD_GOOGLE_ZYDRON
default "gladios" if BOARD_GOOGLE_GLADIOS
+ default "marasov" if BOARD_GOOGLE_MARASOV
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/marasov/include/variant/ec.h b/src/mainboard/google/brya/variants/marasov/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
Patch Set 2:
(1 comment)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/f5663758_2ba80a3c
PS2, Line 26: ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
> Sorry, maybe I'm confused, but isn't this the wrong way around? When verstage is x86 (top branch) yo […]
Build error from Jenkins:
```
arm-eabi-gcc: error: unrecognized command-line option '-mssse3'
```
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Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68954/comment/7c5c81c6_ac65dedf
PS1, Line 11:
> 10 ms and is captured in the prior CL.
Could you also mention that in this CL?
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