coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG defi...
by Johnny Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jonathan Zhang. Hello Jonathan Zhang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69090 to review the following change. Change subject: drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG definitions ...................................................................... drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG definitions Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/xeon_sp/cpx/Makefile.inc D src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/cpx/upd_display.c M src/soc/intel/xeon_sp/skx/upd_display.c M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 7 files changed, 37 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69090/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 8392a03..efda881 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -33,6 +33,16 @@ #include <FirmwareVersionInfo.h> #endif +/* + * Intel FSPs of XEON server platforms define FSPX_CONFIG + * instead of FSP_X_CONFIG, which is expected by coreboot. + */ +#if CONFIG(XEON_SP_COMMON_BASE) +#define FSP_T_CONFIG FSPT_CONFIG +#define FSP_M_CONFIG FSPM_CONFIG +#define FSP_S_CONFIG FSPS_CONFIG +#endif + #pragma pack(pop) #endif diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 0cd267b..d2a1583 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -16,8 +16,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp -CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h - cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h deleted file mode 100644 index 55b2e99..0000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _FSP_UPD_H_ -#define _FSP_UPD_H_ - -/* Rename the FSP UPD structs to what they were historically called on other platforms. */ -#define FSP_T_CONFIG FSPT_CONFIG -#define FSP_M_CONFIG FSPM_CONFIG -#define FSP_S_CONFIG FSPS_CONFIG - -#endif diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index efdce78..6ce5ef5 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -154,7 +154,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - FSPM_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; const struct device *dev; const config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c index ae5eeda..33807d3 100644 --- a/src/soc/intel/xeon_sp/cpx/upd_display.c +++ b/src/soc/intel/xeon_sp/cpx/upd_display.c @@ -12,8 +12,8 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - const FSPM_CONFIG *new; - const FSPM_CONFIG *old; + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; @@ -31,8 +31,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old; old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index 84105dd6..c718a58 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -32,8 +32,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old; old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 0de0fa1..066c2ae 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -553,7 +553,7 @@ /** Offset 0x01E0 **/ UINT8 ReservedMemoryInitUpd[16]; -} FSP_M_CONFIG; +} FSPM_CONFIG; /** Fsp M UPD Configuration **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/69090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Gerrit-Change-Number: 69090 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Hung-Te Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8188/devapc.c: https://review.coreboot.org/c/coreboot/+/69088/comment/2281bc13_2fd53cd2 PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2 don't we need to keep SCP/SSPM in domain2? ref: MT8195: SET32_BITFIELDS(getreg(base, MAS_DOM_0), SCP_SSPM_DOM, DOMAIN_2, CPU_EB_DOM, DOMAIN_2); -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable CPU input gating
by Hung-Te Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable CPU input gating ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69089/comment/fd53ae27_406561cd PS1, Line 7: Disable CPU input gating Fix AP hanging issue due to CPU input gating https://review.coreboot.org/c/coreboot/+/69089/comment/39b792b7_38f911d3 PS1, Line 9: This patch fixes AP hanging issue caused by CPU input gating. The : feature should be disabled by default, so we disable it. If it's by default disabled then we don't need to anything, isn't it? 😊 I think this description should probably be rephrased by 3 topics: - What is CPU input gating - Why keep it enabled would cause AP hang - Why we can disable it (kernel will turn on it? or totally not needed?) For example (I don't know the details so this is only for reference): The CPU input gating is blah blah blah and needs a special driver to blah blah blah. The AP would hang without that. In firmware stage we don't need input gating but it was by default enabled so we have to disable it explicitly. -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:12:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/eventlog: Correct the capitalization for diagnostics types
by Yu-Ping Wu (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69025 ) Change subject: util/eventlog: Correct the capitalization for diagnostics types ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42 Gerrit-Change-Number: 69025 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:05:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in blobs[master]: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
by Yu-Ping Wu (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/69086 ) Change subject: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/blobs/+/69086/comment/e4db19a1_475ee1eb PS2, Line 9: Adding Add File soc/mediatek/mt8188/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/69086/comment/703d2b88_6612023a PS2, Line 3: Adding Add -- To view, visit https://review.coreboot.org/c/blobs/+/69086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04 Gerrit-Change-Number: 69086 Gerrit-PatchSet: 2 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:04:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable CPU input gating
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin. Liju-Clr Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable CPU input gating ...................................................................... soc/mediatek/mt8188: Disable CPU input gating This patch fixes AP hanging issue caused by CPU input gating. The feature should be disabled by default, so we disable it. BUG=none TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/cpu_inputgating.c A src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h M src/soc/mediatek/mt8188/soc.c 4 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/1 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index fc56eb3..30d540c 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += ../common/auxadc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c +ramstage-y += cpu_inputgating.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c diff --git a/src/soc/mediatek/mt8188/cpu_inputgating.c b/src/soc/mediatek/mt8188/cpu_inputgating.c new file mode 100644 index 0000000..321ae55 --- /dev/null +++ b/src/soc/mediatek/mt8188/cpu_inputgating.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/cpu_inputgating.h> + +#define CPU6_IG_EN_REG (MCUSYS_BASE + 0x3308) +#define CPU7_IG_EN_REG (MCUSYS_BASE + 0x3b08) +#define DISABLE_CPU_IG 0xfc000001 + +void disable_cpu_inputgating(void) +{ + write32p(CPU6_IG_EN_REG, DISABLE_CPU_IG); + write32p(CPU7_IG_EN_REG, DISABLE_CPU_IG); +} diff --git a/src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h b/src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h new file mode 100644 index 0000000..89e6a6b --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8188_CPU_INPUTGATING_H +#define SOC_MEDIATEK_MT8188_CPU_INPUTGATING_H + +void disable_cpu_inputgating(void); + +#endif /* SOC_MEDIATEK_MT8188_CPU_INPUTGATING_H */ diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c index bcbea03..ea9b9bf 100644 --- a/src/soc/mediatek/mt8188/soc.c +++ b/src/soc/mediatek/mt8188/soc.c @@ -3,6 +3,7 @@ #include <bootmem.h> #include <console/console.h> #include <device/device.h> +#include <soc/cpu_inputgating.h> #include <soc/devapc.h> #include <soc/dfd.h> #include <soc/dpm.h> @@ -27,6 +28,9 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + + disable_cpu_inputgating(); + dapc_init(); mcupm_init(); sspm_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin. Liju-Clr Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... soc/mediatek/mt8188: Allow MCUPM to access the secure registers This patch fixes AP hanging issue after boot to login shell. DEVAPC enables sideband to allow MCUPM to access the secure registers. Also DEVAPC only allow DOMAIN 0 to access all the non secure registers by default, remove the DOMAIN 2 setting. BUG=none TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/1 diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 260b9ff..a9b7762 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1553,9 +1553,6 @@ /* Side band */ SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS); - /* Master domain */ - SET32_BITFIELDS(getreg(base, MAS_DOM_0), SCP_SSPM_DOM, DOMAIN_2, MCUPM_DOM, DOMAIN_2); - /* Default APC setting */ set_infra_ao_apc(base); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: security/vboot: Update build rules using x86 SHA extension
by Kangheui Won (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Raul Rangel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68953 ) Change subject: security/vboot: Update build rules using x86 SHA extension ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Gerrit-Change-Number: 68953 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:03:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 ) Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate. -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 06:51:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
by EricKY Cheng (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69024 to look at the new patch set (#2). Change subject: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config ...................................................................... mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config Enable Dynamic DPTC support. Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a --- M src/mainboard/google/skyrim/Kconfig.name 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69024/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a Gerrit-Change-Number: 69024 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022