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Liju-Clr Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69088 )
Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
......................................................................
soc/mediatek/mt8188: Allow MCUPM to access the secure registers
This patch fixes AP hanging issue after boot to login shell. DEVAPC
enables sideband to allow MCUPM to access the secure registers. Also
DEVAPC only allow DOMAIN 0 to access all the non secure registers by
default, remove the DOMAIN 2 setting.
BUG=none
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/devapc.c
1 file changed, 18 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/1
diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c
index 260b9ff..a9b7762 100644
--- a/src/soc/mediatek/mt8188/devapc.c
+++ b/src/soc/mediatek/mt8188/devapc.c
@@ -1553,9 +1553,6 @@
/* Side band */
SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS);
- /* Master domain */
- SET32_BITFIELDS(getreg(base, MAS_DOM_0), SCP_SSPM_DOM, DOMAIN_2, MCUPM_DOM, DOMAIN_2);
-
/* Default APC setting */
set_infra_ao_apc(base);
}
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 )
Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate.
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Change subject: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
......................................................................
mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
Enable Dynamic DPTC support.
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a
---
M src/mainboard/google/skyrim/Kconfig.name
1 file changed, 13 insertions(+), 0 deletions(-)
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Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
......................................................................
mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
Define a config for Dynamic DPTC support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3
---
M src/mainboard/google/skyrim/Kconfig
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Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
......................................................................
soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
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Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
---
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
2 files changed, 172 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68470/18
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Change subject: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
......................................................................
soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
The efuse memory address is wrong for MCUPM to access. Adding the
offset to revise the efuse memory address.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M soc/mediatek/mt8188/mcupm.bin
M soc/mediatek/mt8188/mcupm.bin.md5
M soc/mediatek/mt8188/mcupm_release_notes.txt
3 files changed, 21 insertions(+), 1 deletion(-)
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