Attention is currently required from: Bao Zheng, Zheng Bao.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69043 )
Change subject: amdfwtool: Add support for 32M image size
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/69043/comment/5f21300c_a0e9988c
PS1, Line 2302: case 0xFFFA0000: /* Fall through */
: case 0xFFF20000: /* Fall through */
: case 0xFFE20000: /* Fall through */
: case 0xFFC20000: /* Fall through */
: case 0xFF820000: /* Fall through */
: case 0xFF020000: /* Fall through */
Note that this is just not correct.
The EFS is checked at SPI flash offsets, not x86 memory mapped ones.
•1st Address checked (recommended)0xFA0000
•2nd Address checked 0xF20000
•3rd Address checked 0xE20000
•4th Address checked 0xC20000
•5th Address checked 0x820000
•6th Address checked 0x20000
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Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
......................................................................
Patch Set 1:
(1 comment)
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/69088/comment/7f000fb1_5052068d
PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2
> Yes. […]
Sorry for type error.
Yes.
That would cause SCP/SSPM/MCUPM forbidden to access the registers because they are domain 2.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 )
Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > > It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate.
> >
> > in that case https://review.coreboot.org/c/coreboot/+/69041/1/src/soc/intel/meteorlake/p… is also wrong and pmc.c file resource allocator is wrong too https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/pm…
> >
> > Fundamentally you would like to reserve those resources/ranges and doesn’t really matter what index you are giving while reserving (take a look into systemagent.c file where we have given index incrementally) as it's *not* a PCI write into the said *index*, so, it doesn't break anything.
>
> Right, by convention we use indices 0 - 0xf for decoded ranges that are not PCI BARs and the PCI BAR register when it is. The allocator does not care however.
Exactly. Do you suggest me to clean up pmc.c and other as pointed above ? or you would like to take that up? I'm okay to abandon this CL if we are planning to fix things in proper.
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Venkat Thogaru has uploaded a new patch set (#14) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/67673 )
Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
......................................................................
soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
---
M src/mainboard/google/herobrine/romstage.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/memlayout.ld
M src/soc/qualcomm/sc7280/soc.c
4 files changed, 25 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/67673/14
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68389 )
Change subject: WIP:cbfstool: Expand the max size of image to 32M
......................................................................
Patch Set 2: Code-Review-2
(1 comment)
Patchset:
PS2:
I'm pretty sure even AMD hardware does not memory map more than 16M.
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Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
......................................................................
Patch Set 1:
(1 comment)
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/69088/comment/5ccb4322_caedc4d9
PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2
> So, I can say this patch is to bypass the domain setting for SCP_SSPM and MCPUPM for now (i.e. […]
Yes.
That would cause SCP/SSPM/MCUPM forbidden to access the registers because they are no domain 0.
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