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Change subject: soc/mediatek/mt8188: Disable CPU input gating
......................................................................
soc/mediatek/mt8188: Disable CPU input gating
This patch fixes AP hanging issue caused by CPU input gating. The
feature should be disabled by default, so we disable it.
BUG=none
TEST=CPUfreq in kernel test pass.
Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/Makefile.inc
A src/soc/mediatek/mt8188/cpu_inputgating.c
A src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h
M src/soc/mediatek/mt8188/soc.c
4 files changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/2
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
......................................................................
soc/mediatek/mt8188: Allow MCUPM to access the secure registers
This patch fixes AP hanging issue after boot to login shell. DEVAPC
enables sideband to allow MCUPM to access the secure registers. For
MT8188, DEVAPC configures the hardwares(AP/others) as domain 0 by
default and enables no_protection permssions for domain 0. The other
domains are forbidden to access the registers, so remove the DOMAIN 2
setting. Later, we will investigate the requirements from the module
owners to configure the different domains and enable the access
permissions for the different hardwares.
BUG=none
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/devapc.c
1 file changed, 22 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/2
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Hello Rex-BC Chen, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
......................................................................
soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
The efuse memory address is wrong for MCUPM to access. Add the
offset to revise the efuse memory address.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M soc/mediatek/mt8188/mcupm.bin
M soc/mediatek/mt8188/mcupm.bin.md5
M soc/mediatek/mt8188/mcupm_release_notes.txt
3 files changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/86/69086/3
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Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
Patch Set 4: Code-Review+2
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69091 )
Change subject: cbfstool/lz4: Fix compilation issue
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> This is also fixed upstream (https://github.com/lz4/lz4/blob/dev/lib/lz4.c). Should we uprev lz4 instead?
that sounds good actually
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 )
Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > > > It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate.
> > >
> > > in that case https://review.coreboot.org/c/coreboot/+/69041/1/src/soc/intel/meteorlake/p… is also wrong and pmc.c file resource allocator is wrong too https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/pm…
> > >
> > > Fundamentally you would like to reserve those resources/ranges and doesn’t really matter what index you are giving while reserving (take a look into systemagent.c file where we have given index incrementally) as it's *not* a PCI write into the said *index*, so, it doesn't break anything.
> >
> > Right, by convention we use indices 0 - 0xf for decoded ranges that are not PCI BARs and the PCI BAR register when it is. The allocator does not care however.
>
> Exactly. Do you suggest me to clean up pmc.c and other as pointed above ? or you would like to take that up? I'm okay to abandon this CL if we are planning to fix things in proper.
I guess it indeed makes sense to use index 0 for the ACPI IO registers and index 0x10 for the PCH_PWRM_BASE_ADDRESS.
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