coreboot-gerrit November 2022

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[S] Change in coreboot[master]: /: Fix 16-bit read/write PCI_COMMAND register
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Elyes Haouas, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69065 ) Change subject: /: Fix 16-bit read/write PCI_COMMAND register ...................................................................... Patch Set 1: Code-Review-1 (4 comments) Patchset: PS1: What does this exactly fix? Do you if all of these are actually wrong or intended? File src/drivers/usb/pci_ehci.c: https://review.coreboot.org/c/coreboot/+/69065/comment/9ae67cec_924a2a23 PS1, Line 53: pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | : PCI_COMMAND_MASTER); Do you know if it might be intended to leave the upper bits untouched? File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/69065/comment/9cf04606_618b88b2 PS1, Line 985: pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); Do you know if clearing the status registers bit was intended or not here? File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/c/coreboot/+/69065/comment/e01a5975_649de745 PS1, Line 100: dev->command |= PCI_COMMAND_MASTER; : pci_write_config8(dev, PCI_COMMAND, dev->command); Do you know if skip setting the upper 8bit is intended? -- To view, visit https://review.coreboot.org/c/coreboot/+/69065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5b64236cc9998e053e7c3ba5afc338d7367631 Gerrit-Change-Number: 69065 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 11:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask/variants/moli: remove fan setting
by Subrata Banik (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, YH Lin, Nick Vaccaro, Raihow Shi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69094 ) Change subject: mb/google/brask/variants/moli: remove fan setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Gerrit-Change-Number: 69094 Gerrit-PatchSet: 2 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 11:26:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
by Johnny Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Sridhar Siricilla, Shuming Chu (Shuming), Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 ) Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/66579/comment/beaf50d2_c327fe5f PS4, Line 15: get_me_fw_version > I didn't get you, get_me_fw_version() shouldn't be the last HECI command from coreboot to CSE in the […] For our case we call get_me_fw_version after EOP and can see this issue. But I think this part of my commit message shouldn't be important and can be removed, since the Server ME spec requires clearing the interrupt. -- To view, visit https://review.coreboot.org/c/coreboot/+/66579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Gerrit-Change-Number: 66579 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 11:24:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: /: Fix 16-bit read/write PCI_COMMAND register
by Elyes Haouas (Code Review) 01 Nov '22

01 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69065 ) Change subject: /: Fix 16-bit read/write PCI_COMMAND register ...................................................................... /: Fix 16-bit read/write PCI_COMMAND register Change-Id: I6f5b64236cc9998e053e7c3ba5afc338d7367631 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/usb/pci_ehci.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/xeon_sp/bootblock.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/intel/ibexpeak/early_pch.c 8 files changed, 23 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69065/1 diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index fe6eb15..e25e065 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -87,13 +87,13 @@ static void nc_fpga_init(struct device *dev) { void *bar0_ptr = NULL; - uint8_t cmd_reg; + uint16_t cmd_reg; uint32_t cap = 0; /* All we need is mapped to BAR 0, get the address. */ bar0_ptr = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); - cmd_reg = pci_read_config8(dev, PCI_COMMAND); + cmd_reg = pci_read_config16(dev, PCI_COMMAND); /* Ensure BAR0 has a valid value. */ if (!bar0_ptr || !(cmd_reg & PCI_COMMAND_MEMORY)) return; diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 8e85426..f4e1d94 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -50,7 +50,7 @@ pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); - pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_s_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); *base = CONFIG_EHCI_BAR; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2c94ec..7a8c57a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -982,7 +982,7 @@ { if (!disable_cse_idle(dev)) return DEV_IDLE; - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); return DEV_ACTIVE; } @@ -991,7 +991,7 @@ { enable_cse_idle(dev); - pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + pci_and_config16(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); } bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14d..de9abac 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -128,7 +128,7 @@ { pci_devfn_t pci_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); pci_write_config32(pci_dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(pci_dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config16(pci_dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } @@ -173,7 +173,7 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index dd0b0ef..88e5496 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -18,10 +18,10 @@ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5ea09ac..48ff133 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -56,8 +56,8 @@ pch_enable_lpc(); /* Set up P2SB BAR. This is needed for PCR to work */ - uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND); - pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); + uint16_t p2sb_cmd = pci_s_read_config16(PCH_DEV_P2SB, PCI_COMMAND); + pci_s_write_config16(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 88e426a..46662ca 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -98,7 +98,7 @@ } dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_write_config16(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 4df47f3..b449386 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -50,7 +50,7 @@ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + pci_write_config16(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5b64236cc9998e053e7c3ba5afc338d7367631 Gerrit-Change-Number: 69065 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69088/comment/ffefff81_385efe90 PS2, Line 13: forbidden > not allowed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 10:58:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable CPU input gating
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69089 to look at the new patch set (#3). Change subject: soc/mediatek/mt8188: Disable CPU input gating ...................................................................... soc/mediatek/mt8188: Disable CPU input gating This patch fixes AP hanging issue caused by CPU input gating. The feature should be disabled by default, so we disable it. BUG=none TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/cpu_inputgating.c A src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h M src/soc/mediatek/mt8188/soc.c 4 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69088 to look at the new patch set (#3). Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... soc/mediatek/mt8188: Allow MCUPM to access the secure registers This patch fixes AP hanging issue after boot to login shell. DEVAPC enables sideband to allow MCUPM to access the secure registers. For MT8188, DEVAPC configures the hardwares(AP/others) as DOMAIN 0 by default and enables no_protection permssions for DOMAIN 0. The other domains are not allowed to access the registers, so remove the DOMAIN 2 setting. Later, we will investigate the requirements from the module owners to configure the different domains and enable the access permissions for the different hardwares. BUG=none TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by build bot (Jenkins) (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Nico Huber, Julius Werner, Maximilian Brune. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 4: (5 comments) File util/cbfstool/cbfstool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161857): https://review.coreboot.org/c/coreboot/+/68160/comment/67957c20_8fa251e3 PS4, Line 395: * Default decode window lives just below 4G boundary in host space and maps up to a line length of 100 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161857): https://review.coreboot.org/c/coreboot/+/68160/comment/5a6233e8_404f4cd5 PS4, Line 396: * maximum of 16MiB. If the window is smaller than 16MiB, the SPI flash window is mapped line length of 104 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161857): https://review.coreboot.org/c/coreboot/+/68160/comment/28a0209c_a732b52e PS4, Line 399: add_mmap_window(std_window_flash_offset, DEFAULT_DECODE_WINDOW_TOP - std_window_size, std_window_size); line length of 119 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161857): https://review.coreboot.org/c/coreboot/+/68160/comment/6afb4b14_3d538079 PS4, Line 408: ERROR("Flash space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", line length of 135 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161857): https://review.coreboot.org/c/coreboot/+/68160/comment/5f996b20_722a94b8 PS4, Line 418: ERROR("Host space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", line length of 134 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 10:52:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Nico Huber, Julius Werner, Maximilian Brune. Hello build bot (Jenkins), Nico Huber, Julius Werner, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68160 to look at the new patch set (#4). Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... util/cbfstool: Add a new mechanism to provide a memory mapped This replaces the mechanism with --ext-win-base --ext-win-size with a more generic mechanism where cbfstool can be provided with an arbitrary memory map. This will be useful for AMD platforms with flash sizes larger than 16M where only the lower 16M half gets memory mapped below 4G. Also on Intel system the IFD allows for a memory map where the "top of flash" != "below 4G". This is for instance the case by default on Intel APL. TEST: google/brya build for chromeos which used --ext-win-base remains the same after this change with BUILD_TIMELESS=1. Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/fast_spi/Makefile.inc M util/cbfstool/cbfstool.c 2 files changed, 144 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/68160/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Nico Huber, Julius Werner, Maximilian Brune. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 3: (3 comments) File src/soc/intel/common/block/fast_spi/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68160/comment/23226dab_799b1100 PS3, Line 91: $(call int-subtract, $(CONFIG_ROM_SIZE) 0x1000000) > Can we factor this term out into a separate variable (e.g. […] Done File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/68160/comment/d33a86e7_f3c5ab30 PS3, Line 317: static int next_window; > nit: namespace a bit better since it's a global (e.g. […] Done https://review.coreboot.org/c/coreboot/+/68160/comment/97cf10e1_86a45d0e PS3, Line 338: MMAP_SIZE > nit: That's a bit of an odd way to name fields in an array, particularly since these constants are g […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 10:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2022