coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/amd/mendocino/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69070 ) Change subject: soc/amd/mendocino/data_fabric: Add register bitslice struct ...................................................................... soc/amd/mendocino/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 --- M src/soc/amd/mendocino/include/soc/data_fabric.h 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69070/1 diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index a73bc42..a1a1f4e 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -12,4 +12,32 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 4; /* [ 7.. 4] */ + uint32_t : 8; /* [15.. 8] */ + uint32_t np : 1; /* [16..16] */ + uint32_t : 15; /* [31..17] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + + #endif /* AMD_MENDOCINO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Gerrit-Change-Number: 69070 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/picasso/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69069 ) Change subject: soc/amd/picasso/data_fabric: Add register bitslice struct ...................................................................... soc/amd/picasso/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 --- M src/soc/amd/picasso/include/soc/data_fabric.h 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/69069/1 diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 054ca89..f71abe0 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -14,6 +14,33 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 8; /* [11.. 4] */ + uint32_t np : 1; /* [12..12] */ + uint32_t : 19; /* [31..13] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + + #define D18F0_VGAEN 0x80 #define VGA_ADDR_ENABLE BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/69069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Gerrit-Change-Number: 69069 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/cezanne/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69068 ) Change subject: soc/amd/cezanne/data_fabric: Add register bitslice struct ...................................................................... soc/amd/cezanne/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff --- M src/soc/amd/cezanne/include/soc/data_fabric.h 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/69068/1 diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 1808df3..0a89971 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -12,4 +12,31 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 10; /* [13.. 4] */ + uint32_t : 2; /* [15..14] */ + uint32_t np : 1; /* [16..16] */ + uint32_t : 15; /* [31..17] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + #endif /* AMD_CEZANNE_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Gerrit-Change-Number: 69068 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common
by Fred Reitberger (Code Review) 01 Nov '22

01 Nov '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69067 ) Change subject: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common ...................................................................... soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/data_fabric.c M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/data_fabric.c M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/data_fabric.c M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/morgana/chip.c M src/soc/amd/morgana/data_fabric.c M src/soc/amd/morgana/include/soc/data_fabric.h M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/include/soc/data_fabric.h 17 files changed, 107 insertions(+), 480 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/69067/1 diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index e4aa704..efef2f1 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index 5dc0f99..6a34a07 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -1,102 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 27444be..1808df3 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -12,6 +12,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_CEZANNE_DATA_FABRIC_H */ diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 0fcee36..f1a067f 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -2,7 +2,9 @@ #include <amdblocks/data_fabric.h> #include <amdblocks/pci_devs.h> +#include <arch/hpet.h> #include <console/console.h> +#include <cpu/x86/lapic_def.h> #include <device/pci_ops.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> @@ -82,3 +84,89 @@ } return -1; } + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; + + data_fabric_print_mmio_conf(); + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) + continue; /* not enabled */ + + base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); + continue; + } + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + else + data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); + } + + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "cannot configure region as NP\n"); + return; + } + + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP + | DF_MMIO_WE | DF_MMIO_RE); + + data_fabric_print_mmio_conf(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 604c24e..5cc7f48 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -45,5 +45,6 @@ void data_fabric_print_mmio_conf(void); void data_fabric_disable_mmio_reg(unsigned int reg); int data_fabric_find_unused_mmio_reg(void); +void data_fabric_set_mmio_np(void); #endif /* AMD_BLOCK_DATA_FABRIC_H */ diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index b0b90ee..9e9ee9e 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -2,13 +2,13 @@ /* TODO: Update for Glinda */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/glinda/data_fabric.c b/src/soc/amd/glinda/data_fabric.c index 822d5a9..3bc0b6d 100644 --- a/src/soc/amd/glinda/data_fabric.c +++ b/src/soc/amd/glinda/data_fabric.c @@ -3,103 +3,10 @@ /* TODO: Update for Glinda */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 4abbb3d..0bb9561 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -14,6 +14,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_GLINDA_DATA_FABRIC_H */ diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 99e33ce..83a485f 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -2,13 +2,13 @@ /* TODO: Check if this is still correct */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c index f1ee4df..2569da8 100644 --- a/src/soc/amd/mendocino/data_fabric.c +++ b/src/soc/amd/mendocino/data_fabric.c @@ -1,105 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index c7727bb..a73bc42 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -12,6 +12,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_MENDOCINO_DATA_FABRIC_H */ diff --git a/src/soc/amd/morgana/chip.c b/src/soc/amd/morgana/chip.c index 086211e..13d2638 100644 --- a/src/soc/amd/morgana/chip.c +++ b/src/soc/amd/morgana/chip.c @@ -2,13 +2,13 @@ /* TODO: Update for Morgana */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/morgana/data_fabric.c b/src/soc/amd/morgana/data_fabric.c index 2f72e3a..6c02d21 100644 --- a/src/soc/amd/morgana/data_fabric.c +++ b/src/soc/amd/morgana/data_fabric.c @@ -3,103 +3,10 @@ /* TODO: Update for Morgana */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/morgana/include/soc/data_fabric.h b/src/soc/amd/morgana/include/soc/data_fabric.h index eba4cd8..c210e47 100644 --- a/src/soc/amd/morgana/include/soc/data_fabric.h +++ b/src/soc/amd/morgana/include/soc/data_fabric.h @@ -14,6 +14,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_MORGANA_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 37e62e2..fc30af9 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index ddc280b..a251158 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -1,102 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 5533433..054ca89 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -49,6 +49,4 @@ #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ + D18F0_DRAM_LIMIT0) -void data_fabric_set_mmio_np(void); - #endif /* AMD_PICASSO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Gerrit-Change-Number: 69067 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/*: Add PSP verstage minbuild
by Balázs Vinarz (Code Review) 01 Nov '22

01 Nov '22

Balázs Vinarz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59585 ) Change subject: soc/amd/*: Add PSP verstage minbuild ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Is it possible that I'm not able to boot up my Ryzen powered Chromebook without this patch? https://ticket.coreboot.org/issues/436?issue_count=143&issue_position=1&nex… -- To view, visit https://review.coreboot.org/c/coreboot/+/59585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 Gerrit-Change-Number: 59585 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 01 Nov 2022 14:25:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
by Venkat Thogaru (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Shelley Chen. Venkat Thogaru has uploaded a new patch set (#17) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/67673 ) Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage ...................................................................... soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 4 files changed, 25 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/67673/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/67673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Gerrit-Change-Number: 67673 Gerrit-PatchSet: 17 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
by Venkat Thogaru (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Venkat Thogaru, Paul Menzel, Sudheer Amrabadi. Venkat Thogaru has uploaded a new patch set (#10) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68385 ) Change subject: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro ...................................................................... soc/qualcomm/sc7280: Update Skuid to support pro/non-pro Tranferring a bit to DC through Skuid to update the regulator node in order to support pro and non-pro BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad(a)quicinc.com> Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07 --- M src/mainboard/google/herobrine/boardid.c 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68385/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/68385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07 Gerrit-Change-Number: 68385 Gerrit-PatchSet: 10 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
by Venkat Thogaru (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Shelley Chen, Taniya Das, Venkat Thogaru, Julius Werner, Sudheer Amrabadi. Venkat Thogaru has uploaded a new patch set (#9) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot ...................................................................... soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot The API socinfo_pro_part is added to help to differentiate between PRO and NON_PRO SKUs. Returns 1 for Pro and 0 for NON_PRO SKUs. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca --- M src/soc/qualcomm/sc7280/include/soc/socinfo.h M src/soc/qualcomm/sc7280/socinfo.c 2 files changed, 90 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 9 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Yidi Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 14:23:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
by Sudheer Amrabadi (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Shelley Chen. Sudheer Amrabadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67673 ) Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage ...................................................................... Patch Set 16: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67673/comment/24350561_291b4b9d PS3, Line 13: TEST=Validated on qualcomm sc7280 development board > updated commit message with relavant test result and more description Ack Patchset: PS16: can you please review once File src/soc/qualcomm/sc7280/memlayout.ld: https://review.coreboot.org/c/coreboot/+/67673/comment/238fa220_13a458ff PS3, Line 51: 140K > Able to optimize this memory to 102 Kb, and below that we have observed device crashes. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/67673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Gerrit-Change-Number: 67673 Gerrit-PatchSet: 16 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 14:17:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2022