coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/corsola: Add new board 'voltorb'
by Yu-Ping Wu (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Knox Chiou, Chen-Tsung Hsieh, Mars Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69095 ) Change subject: mb/google/corsola: Add new board 'voltorb' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Gerrit-Change-Number: 69095 Gerrit-PatchSet: 2 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 13:04:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask/variants/moli: remove fan setting
by Zhuohao Lee (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, YH Lin, Nick Vaccaro, Raihow Shi. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69094 ) Change subject: mb/google/brask/variants/moli: remove fan setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Gerrit-Change-Number: 69094 Gerrit-PatchSet: 2 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 12:36:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/sbom: Add SBOM Documentation
by Nicholas Chin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Patrick Rudolph, Richard Hughes, Angel Pons, Maximilian Brune. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68995 ) Change subject: Documentation/sbom: Add SBOM Documentation ...................................................................... Patch Set 6: (1 comment) File Documentation/sbom/sbom_generation.plantuml: PS6: > What does this file do? It appears to be the source for the diagram, written for a tool called plantuml. That tool does support outputting an SVG, which goes back to your other comment about the actual image file. -- To view, visit https://review.coreboot.org/c/coreboot/+/68995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Gerrit-Change-Number: 68995 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Richard Hughes <richard(a)hughsie.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 12:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn)
by build bot (Jenkins) (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Alexander Couzens. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69066 ) Change subject: mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn) ...................................................................... Patch Set 1: (122 comments) File src/mainboard/asus/am1i-a/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5185ffc0_87bb203f PS1, Line 23: /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ line length of 121 exceeds 114 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/0e60f0d1_b8c7cd88 PS1, Line 24: {0x00, PCI_DEVFN(0x1, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, line length of 118 exceeds 115 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f9364ce4_1e8c3f3d PS1, Line 25: {0x00, PCI_DEVFN(0x02, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, line length of 119 exceeds 116 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/20ef9a8c_824451c1 PS1, Line 26: {0x00, PCI_DEVFN(0x10, 0), {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, line length of 119 exceeds 117 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/0006ca81_c168a1ff PS1, Line 27: {0x00, PCI_DEVFN(0x11, 0), {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, line length of 119 exceeds 118 columns File src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/1b620a13_a23a0cae PS1, Line 21: {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/b3c3f693_f1507da8 PS1, Line 22: {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/eea95bc8_f94c0cc1 PS1, Line 23: {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/9e6be685_4bba67d2 PS1, Line 24: {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8887a5c4_7b1d5280 PS1, Line 25: {0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/169f5a1b_2e3b5297 PS1, Line 26: {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/1d3f3b30_87301ccc PS1, Line 27: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/asus/p2b/variants/p2b/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/4031742f_c14c60b6 PS1, Line 21: {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8c123924_9ab25efa PS1, Line 22: {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/7469bac7_1b7962c6 PS1, Line 23: {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/44777030_06883fd0 PS1, Line 24: {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/853b17e1_8b69a8de PS1, Line 25: {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/42bf4038_9e8e309d PS1, Line 26: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/4316521d_c92dc5a2 PS1, Line 21: {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f69c36e5_44b3ab5e PS1, Line 22: {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/12eb1e6c_445697e2 PS1, Line 23: {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5e64df83_edd07e42 PS1, Line 24: {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/942445e2_979404de PS1, Line 25: {0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/bdce7950_bc051608 PS1, Line 26: {0x00,PCI_DEVFN(0x0e, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/70d4faa8_af0ef9be PS1, Line 27: {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/3fdb0323_ab385903 PS1, Line 28: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/emulation/qemu-i440fx/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/bc29cf3f_b90881ce PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/242eb649_13acc1fd PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/b21882e6_fb921d8b PS1, Line 23: {0x00,PCI_DEVFN(0x03, 0), {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/2d9a54b0_70614549 PS1, Line 24: {0x00,PCI_DEVFN(0x04, 0), {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c2bd95c7_c87644df PS1, Line 25: {0x00,PCI_DEVFN(0x05, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/de4a3406_156b0b49 PS1, Line 26: {0x00,PCI_DEVFN(0x06, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/getac/p470/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d71cfca4_708c5088 PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/110eb6db_6ec76cc9 PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a2b992b9_5924993b PS1, Line 23: {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/2b4b83ec_339c7571 PS1, Line 24: {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8693b716_546f0530 PS1, Line 25: {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5e29792f_42ff81fa PS1, Line 26: {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d9fcddd4_a04b16eb PS1, Line 27: {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/80ebebc7_9f06c1da PS1, Line 28: {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/09f5b0ac_d7855534 PS1, Line 29: {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/4ce124bf_d4371562 PS1, Line 30: {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d7668434_f4269a6a PS1, Line 31: {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/e18be361_59a9df34 PS1, Line 32: {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/83776cfa_6bf2af6f PS1, Line 33: {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/26c4ff72_e6959037 PS1, Line 34: {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/bba7c83c_baebbeda PS1, Line 35: {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/10273366_aadd5bc6 PS1, Line 36: {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/989a84fe_c014eb69 PS1, Line 37: {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/76add2bc_4b764942 PS1, Line 38: {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/ibase/mb899/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/031f10f9_b372f81c PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/adc8d02d_acbeb14b PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c7384566_3c4db15f PS1, Line 23: {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/3c1b806e_505dc3f4 PS1, Line 24: {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8ffc8e51_3a9c19bf PS1, Line 25: {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5c1b7f9b_20409572 PS1, Line 26: {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d09271c3_ec8c1a84 PS1, Line 27: {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8111c716_9cdb34cd PS1, Line 28: {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/4a434b69_a01f1bfa PS1, Line 29: {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/e2f595b9_0ad55ac9 PS1, Line 30: {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/100abcfc_5f2caeac PS1, Line 31: {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a7aa0c17_9d79bbf3 PS1, Line 32: {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a8692d64_42bed439 PS1, Line 33: {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/e0de3b61_e6948114 PS1, Line 34: {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c6720bbe_a3a1cceb PS1, Line 35: {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/2020bb70_5a079e3b PS1, Line 36: {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d28fed0c_970f9c10 PS1, Line 37: {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/e6a1d065_b74d7ffa PS1, Line 38: {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/intel/d945gclf/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/36bcad06_939cd32f PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/da8ad386_5a04335b PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/856bf62a_b7ec45fb PS1, Line 23: {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/9f604963_5d32d8ff PS1, Line 24: {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f4faeeb8_a39953e3 PS1, Line 25: {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/9b12b46b_ad39acc3 PS1, Line 26: {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c4a74fd8_dc101fb1 PS1, Line 27: {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/21bfb423_157111e4 PS1, Line 28: {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/16e2facd_3d8753c0 PS1, Line 29: {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c440c7eb_ffda8759 PS1, Line 30: {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/0582c993_0ea83dc5 PS1, Line 31: {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d102656f_dabd1fd9 PS1, Line 32: {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/882e064f_4c6c972f PS1, Line 33: {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/29b76a8d_573027b9 PS1, Line 34: {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/439bb3d7_4e816ee9 PS1, Line 35: {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5bf4c5f2_cf8ccc16 PS1, Line 36: {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a1ee8d1d_80b87ab4 PS1, Line 37: {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8f912fee_20ba70ae PS1, Line 38: {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/kontron/986lcd-m/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/cbf86aee_1d075449 PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f27542fa_e8134d06 PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/defdd7a4_c65f407a PS1, Line 23: {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/aef5fa9e_3ba44bc1 PS1, Line 24: {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/d9bfe28d_124f80f6 PS1, Line 25: {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/350ff2c6_2a8878a4 PS1, Line 26: {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8382822d_a45f791a PS1, Line 27: {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/6824ac51_697f632c PS1, Line 28: {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/70da4639_045adeb5 PS1, Line 29: {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/13bd2e69_3d9a144e PS1, Line 30: {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f1fb8a52_5aa48179 PS1, Line 31: {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/385f5e9a_c56d2deb PS1, Line 32: {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/31b96d69_514f5b25 PS1, Line 33: {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a9d718c8_40732147 PS1, Line 34: {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f486e7dd_4f967718 PS1, Line 35: {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/a34f5410_a0f3e47f PS1, Line 36: {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8f747655_7723e0e3 PS1, Line 37: {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/5e769808_df83fe00 PS1, Line 38: {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, space required after that ',' (ctx:VxV) File src/mainboard/roda/rk886ex/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/59cf91b6_356c4255 PS1, Line 21: {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/715eb15f_1a52de86 PS1, Line 22: {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/6032d8e1_2a0a32d1 PS1, Line 23: {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/e392bcd3_efcf0349 PS1, Line 24: {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/da1778a4_72689f2b PS1, Line 25: {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/c5585b8f_98b90601 PS1, Line 26: {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/718d8f0c_15d244cf PS1, Line 27: {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f020f87f_2cfe6d9e PS1, Line 28: {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/0ebb3914_95d4b3d6 PS1, Line 29: {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/8f5fa252_c0f204e2 PS1, Line 30: {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/90a9753d_210109b1 PS1, Line 31: {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/928677ea_feeef9ec PS1, Line 32: {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/31486310_f2e7314d PS1, Line 33: {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/10dfa58e_7d5d4b2f PS1, Line 34: {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/2756b4ce_7a2abf43 PS1, Line 35: {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/cdc9d5c1_0b85d6b6 PS1, Line 36: {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/f1adb1ab_22ce459f PS1, Line 37: {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161862): https://review.coreboot.org/c/coreboot/+/69066/comment/fd623774_8070cf3a PS1, Line 38: {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/69066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic97bf7c8f04edbb56f200c34060d22a8c5fb7ec2 Gerrit-Change-Number: 69066 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 01 Nov 2022 12:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn)
by Elyes Haouas (Code Review) 01 Nov '22

01 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69066 ) Change subject: mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn) ...................................................................... mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn) Change-Id: Ic97bf7c8f04edbb56f200c34060d22a8c5fb7ec2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/asus/am1i-a/irq_tables.c M src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c M src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c M src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c M src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c M src/mainboard/asus/p2b/variants/p2b/irq_tables.c M src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c M src/mainboard/biostar/am1ml/irq_tables.c M src/mainboard/emulation/qemu-i440fx/irq_tables.c M src/mainboard/getac/p470/irq_tables.c M src/mainboard/ibase/mb899/irq_tables.c M src/mainboard/intel/d945gclf/irq_tables.c M src/mainboard/kontron/986lcd-m/irq_tables.c M src/mainboard/lenovo/x60/irq_tables.c M src/mainboard/roda/rk886ex/irq_tables.c 15 files changed, 226 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/69066/1 diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index 3e0606e..832b20a 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x14 << 3) | 0x3, /* Interrupt router dev */ + PCI_DEVFN(0x14, 0x03), /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ 0x1002, /* Vendor */ 0x439d, /* Device */ @@ -19,17 +20,17 @@ */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0x1, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x02, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x10, 0), {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x11, 0), {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x12, 0), {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x13, 0), {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x14, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x16, 0), {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, PCI_DEVFN(0, 0), {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x02, PCI_DEVFN(0, 0), {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c index 358260b..f4ab399 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -16,13 +17,13 @@ 0x54, /* Checksum */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c index 0b78c0b..b732e81 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -16,14 +17,14 @@ 0x36, /* Checksum */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x06, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c index 8c57ca6..3920aba 100644 --- a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -16,14 +17,14 @@ 0xf9, /* Checksum */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, - {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c index 1bad19b..76f7e3d 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -19,15 +20,15 @@ */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x06, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x07, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c index 8967f84..2f2f534 100644 --- a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -16,13 +17,13 @@ 0x54, /* Checksum */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c index 39c2058..e80e588 100644 --- a/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ + PCI_DEVFN(0x04, 0), /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -16,15 +17,15 @@ 0x95, /* Checksum */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, - {0x00,(0x0e << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, - {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,PCI_DEVFN(0x0e, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, + {0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index 9d0bd60..00342b8 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32 + 16 * 10, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x14 << 3) | 0x3, /* Interrupt router dev */ + PCI_DEVFN(0x14, 0x03), /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ 0x1002, /* Vendor */ 0x439d, /* Device */ @@ -19,17 +20,17 @@ */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x00 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, - {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x11 << 3) | 0x0, {{0x04, 0xdab8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x12, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0, 0), {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x1, 0), {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x02, 0), {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x14, 0), {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x12, 0), {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x13, 0), {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x16, 0), {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x10, 0), {{0x03, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, PCI_DEVFN(0x11, 0), {{0x04, 0xdab8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, PCI_DEVFN(0, 0), {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x12, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c index e288afd..1ee0320 100644 --- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x01 << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x01, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ @@ -17,12 +18,12 @@ /* clang-format off */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x02 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x03 << 3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x04 << 3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x05 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x06 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, + {0x00,PCI_DEVFN(0x02, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, + {0x00,PCI_DEVFN(0x03, 0), {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, + {0x00,PCI_DEVFN(0x04, 0), {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, + {0x00,PCI_DEVFN(0x05, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, + {0x00,PCI_DEVFN(0x06, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index 1d5c97e..ade196b 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x1f, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -16,25 +17,25 @@ 0xf, /* u8 checksum. */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index 7974422..150bc2a 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x1f, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b9, /* Device */ @@ -16,25 +17,25 @@ 0xf, /* u8 checksum. */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 - {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 + {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c index 4e1f6b9..1e261b19 100644 --- a/src/mainboard/intel/d945gclf/irq_tables.c +++ b/src/mainboard/intel/d945gclf/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x1f, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -16,25 +17,25 @@ 0xf, /* u8 checksum. */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 2545aa8..5d4fedc 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x1f, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -16,25 +17,25 @@ 0xf, /* u8 checksum. */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ - {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ - {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ + {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ + {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } /* clang-format on */ }; diff --git a/src/mainboard/lenovo/x60/irq_tables.c b/src/mainboard/lenovo/x60/irq_tables.c index b39a440..996f8f3 100644 --- a/src/mainboard/lenovo/x60/irq_tables.c +++ b/src/mainboard/lenovo/x60/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32 + 16 * 15, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ + PCI_DEVFN(0x1f, 0), /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ @@ -19,21 +20,21 @@ */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ - {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ - {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ - {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ - {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ - {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ - {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ - {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ - {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ - {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ - {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ - {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ - {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, PCI_DEVFN(0x02, 0), {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ + {0x00, PCI_DEVFN(0x1b, 0), {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ + {0x00, PCI_DEVFN(0x1c, 0), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ + {0x00, PCI_DEVFN(0x1c, 0x1), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ + {0x00, PCI_DEVFN(0x1c, 0x2), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ + {0x00, PCI_DEVFN(0x1c, 0x3), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ + {0x00, PCI_DEVFN(0x1d, 0), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ + {0x00, PCI_DEVFN(0x1d, 0x1), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ + {0x00, PCI_DEVFN(0x1d, 0x2), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ + {0x00, PCI_DEVFN(0x1d, 0x3), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ + {0x00, PCI_DEVFN(0x1e, 0), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ + {0x00, PCI_DEVFN(0x1f, 0), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ + {0x00, PCI_DEVFN(0x1f, 0x1), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ + {0x00, PCI_DEVFN(0x1f, 0x2), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ } /* clang-format on */ }; diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index bacf5fe..ffbbcc9 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> +#include <device/pci_def.h> static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + PCI_DEVFN(0x1f, 0), /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -16,25 +17,25 @@ 0xf, /* u8 checksum. */ /* clang-format off */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ - {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ - {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + /* bus,PCI_DEVFN(dev, fn), {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ + {0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ + {0x02,PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } /* clang-format on */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic97bf7c8f04edbb56f200c34060d22a8c5fb7ec2 Gerrit-Change-Number: 69066 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim: Disable SD ASPM
by Fred Reitberger (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Martin Roth, Tim Van Patten, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68940 ) Change subject: mb/google/skyrim: Disable SD ASPM ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Patchset: PS5: The concern is SD card reader power consumption on the other variants, but as this is a short-term patch until b:245550573 is fixed, I'm fine with it. File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/68940/comment/b74364ed_88f82ae0 PS5, Line 31: .link_aspm = ASPM_DISABLED, Suggestion: add the same TODO comment as the SSD entry has -- To view, visit https://review.coreboot.org/c/coreboot/+/68940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Gerrit-Change-Number: 68940 Gerrit-PatchSet: 5 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Nov 2022 12:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya : Set EPP value for Vell board
by Subrata Banik (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Gaggery Tsai, Kedar J. Karanje, Tarun Tuli, Jérémy Compostella, Tim Wawrzynczak, Sridhar Siricilla, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68900 ) Change subject: mb/google/brya : Set EPP value for Vell board ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68900/comment/1ae81006_5b295220 PS3, Line 11: TEST=Verified code build for Vell board > Please refer b:215526166 for details. You should specify what is being test with this CL and benefits beyond just mentioning the bug number. In short, you can just mention the PLT test results w/ and w/o the CL, so, the impact of this CL is justified. -- To view, visit https://review.coreboot.org/c/coreboot/+/68900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Gerrit-Change-Number: 68900 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 12:06:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya : Set EPP value for Vell board
by Sridhar Siricilla (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Gaggery Tsai, Kedar J. Karanje, Subrata Banik, Jérémy Compostella, Tim Wawrzynczak, Kane Chen. Hello Gaggery Tsai, build bot (Jenkins), Kedar J. Karanje, Subrata Banik, Jérémy Compostella, Tim Wawrzynczak, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68900 to look at the new patch set (#4). Change subject: mb/google/brya : Set EPP value for Vell board ...................................................................... mb/google/brya : Set EPP value for Vell board The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell system demonstrated better power improvement without sacrificing the performance. Branch=firmware-brya-14505.B BUG=b:215526166 TEST=Verified code build for Vell board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/68900/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Gerrit-Change-Number: 68900 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Kyle Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Frank Chu. Kyle Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69052 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/69052/comment/acf79bcc_263b4109 PS2, Line 292: select BOARD_GOOGLE_BASEBOARD_BRYA Add a new line at the end of the file. -- To view, visit https://review.coreboot.org/c/coreboot/+/69052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Gerrit-Change-Number: 69052 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyle Lin <kylelinck(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 11:52:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: inc/dev:Add some pcie definitions
by Shuming Chu (Shuming) (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tim Chu. Hello Tim Chu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69106 to review the following change. Change subject: inc/dev:Add some pcie definitions ...................................................................... inc/dev:Add some pcie definitions * Add DPC related definitions. * Add AER related definitions. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 --- M src/include/device/pci_def.h 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69106/1 diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 64c1ac2..39369f8 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -478,6 +478,7 @@ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ +#define PCI_ERR_SURPRISE_DN 0x00000020 /* Surprise Down */ #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ @@ -487,6 +488,8 @@ #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ +#define PCI_ERR_UNC_INTL_ERR 0x00400000 /* Uncorrectable Internal Error */ +#define PCI_ERR_UNC_POISON_BLK 0x04000000 /* Poisoned TLP Egress Blocked */ #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ /* Same bits as above */ #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ @@ -497,6 +500,9 @@ #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ +#define PCI_ERR_COR_ANF 0x00002000 /* Advisory Non-Fatal Error */ +#define PCI_ERR_COR_INTL_ERR 0x00004000 /* Corrected Internal Error */ +#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow Error */ #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ /* Same bits as above */ #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ @@ -507,10 +513,23 @@ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ +#define PCI_EXP_ROOT_CERE 0x0001 /* Correctable Error Reporting Enable */ +#define PCI_EXP_ROOT_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ +#define PCI_EXP_ROOT_FERE 0x0004 /* Fatal Error Reporting Enable */ #define PCI_ERR_ROOT_STATUS 48 #define PCI_ERR_ROOT_COR_SRC 52 #define PCI_ERR_ROOT_SRC 54 +/* DPC Capability Structure */ +#define PCIE_DPC_CAP_ID 0x1d +#define PCIE_DPC_CTL 0x6 +#define DPC_TRIGGER_EN (1 << 1) +#define DPC_INT_EN (1 << 3) +#define DPC_ERR_COR_EN (1 << 4) +#define DPC_POISON_TLP (1 << 5) +#define PCIE_DPC_RP_PIO_MASK 0x10 +#define PCIE_DPC_SEV 0x14 + /* Virtual Channel */ #define PCI_VC_PORT_REG1 4 #define PCI_VC_PORT_REG2 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/69106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 Gerrit-Change-Number: 69106 Gerrit-PatchSet: 1 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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