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Hello build bot (Jenkins), Angel Pons, Nick Vaccaro, Ricky Chang, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/gladios: use RPL FSP headers
......................................................................
mb/google/brya/var/gladios: use RPL FSP headers
To support an RPL SKU on gladios, gladios must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for gladios so that it will use the RPL
FSP headers for gladios.
BUG=b:239513596
BRANCH=None
TEST=FW_NAME=gladios emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68570/2
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69090 )
Change subject: soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/cpx/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69090/comment/a9d76c90_c42252e8
PS1, Line 19: CPPFLAGS_common += -i
> You now need to include soc_binding.h in the right files 'above' other header files. […]
Changed to use a CPP flag instead.
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Attention is currently required from: Johnny Lin, Christian Walter, Andrey Petrov, Tim Chu.
Hello Jonathan Zhang, Christian Walter, Arthur Heymans, Andrey Petrov, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69090
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
......................................................................
soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/Makefile.inc
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/cpx/upd_display.c
R src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/skx/upd_display.c
M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
7 files changed, 34 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69090/2
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