coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: amdfwtool: Add support for 32M image size
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Bao Zheng, Zheng Bao. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69043 ) Change subject: amdfwtool: Add support for 32M image size ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/69043/comment/c956369f_277fb8e5 PS1, Line 2308: case 0xFE020000: /* Fall through */ Does the hardware work this way? I think only 16M at most gets memory mapped. -- To view, visit https://review.coreboot.org/c/coreboot/+/69043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica050dfecd258fdd6717c308907d7d4d2e85b926 Gerrit-Change-Number: 69043 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 01 Nov 2022 07:56:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG defi...
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Andrey Petrov, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69090 ) Change subject: drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG definitions ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/cpx/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69090/comment/ade05bc7_b74149a8 PS1, Line 19: CPPFLAGS_common += -i You now need to include soc_binding.h in the right files 'above' other header files. Because needing an explicit order in header files is painful (and sometimes not possible if it's common code) a CPP flag is easier to deal with. -- To view, visit https://review.coreboot.org/c/coreboot/+/69090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Gerrit-Change-Number: 69090 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:55:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Yidi Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8188/devapc.c: https://review.coreboot.org/c/coreboot/+/69088/comment/0d9ba746_c267bf4b PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2 > For MT8188, DEVAPC configures the hardwares(AP/others) as domain 0 by default and enables no_protect […] So, I can say this patch is to bypass the domain setting for SCP_SSPM and MCPUPM for now (i.e. keep their domain settings in DOMAIN 0), right ? -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:52:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
by EricKY Cheng (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Caveh Jalali, Paul Menzel, Tim Wawrzynczak, Tim Van Patten, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal ...................................................................... Patch Set 21: (15 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68471/comment/ee232ea6_0b580960 PS10, Line 7: common/acpi/dptc: Dynamic Thermal Table Switching Proposal > Please make this a statement by adding a verb (in imperative mood) [1]. […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/62a15150_d3a8ee28 PS10, Line 9: Thermal table switches to different modes to meet 6 : user experience. > Please use 72 characters per line. […] Done Patchset: PS21: Hi all, Update new patch based on below fixed *Space before “==” *“Lid on” change to “Lid open” *Remove debug message *Combine STTB block *Update commit title and description And follow the suggestions, re-design the table switch method by adding PRTN in ec.asl when FEATURE_DYNAMIC_DPTC is configure (We can discuss if it should replace by TNCA) BR, Eric KY Cheng File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/5a70a7dc_4f23f510 PS10, Line 38: //Desktop + Lid on > Please use C89 comment style (as above). (A space is missing after `//` too. […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/5725d1c1_bebf16e0 PS10, Line 38: Lid on > Does "Lid on" mean "lid open"? Done https://review.coreboot.org/c/coreboot/+/68471/comment/4dc1a40c_06d49799 PS10, Line 39: STTB==0 > style: Add spaces around the `==`. Done https://review.coreboot.org/c/coreboot/+/68471/comment/bafc24cd_6bbaccbe PS10, Line 43: Printf ("EC : Desktop + Lid on") > While these are fine for debug, we don't want/need to output these types of "Desktop + Lid on" state […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/00bb9fd6_98484115 PS10, Line 44: //over 50 > After chatting with Raul, he pointed out that storing the previously applied table ID in a `Name`d o […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/88ef6f59_b8ca0939 PS10, Line 45: 0x7B > Ah, 50C is 122F, so maybe this is off by 1? Done https://review.coreboot.org/c/coreboot/+/68471/comment/f4ff1511_25c60ce7 PS10, Line 47: Printf ("EC : Table B") > All of these "Table X" log statements should be moved into the `acpigen_write_alib_dptc_*` methods i […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/3ff0b69f_f1cd507a PS10, Line 60: } : : If (\_SB.PCI0.LPCB.EC0.STTB==0) : { > Combine these blocks, so we don't need to read `STTB` multiple times. Done https://review.coreboot.org/c/coreboot/+/68471/comment/ae6d1f8d_79d4780e PS10, Line 83: } : If (\_SB.PCI0.LPCB.EC0.STTB==1) : { > Make this an `Else`. Done https://review.coreboot.org/c/coreboot/+/68471/comment/5b5dc9b5_c84d237a PS10, Line 108: Printf ("EC: DPTC Call End(Should not show here)") > This can be removed. Done File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/1fed476b_fffa57ef PS12, Line 44: TIN4 > These are all device specific values. […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/7abf33dd_8693d258 PS12, Line 51: 0x76 > Please use decimal values instead of hex Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 21 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:51:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 ) Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate. > > in that case https://review.coreboot.org/c/coreboot/+/69041/1/src/soc/intel/meteorlake/p… is also wrong and pmc.c file resource allocator is wrong too https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/pm… > > Fundamentally you would like to reserve those resources/ranges and doesn’t really matter what index you are giving while reserving (take a look into systemagent.c file where we have given index incrementally) as it's *not* a PCI write into the said *index*, so, it doesn't break anything. Right, by convention we use indices 0 - 0xf for decoded ranges that are not PCI BARs and the PCI BAR register when it is. The allocator does not care however. -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:50:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Hung-Te Lin (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8188/devapc.c: https://review.coreboot.org/c/coreboot/+/69088/comment/d087da94_c4db925a PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2 > For MT8188, DEVAPC configures the hardwares(AP/others) as domain 0 by default and enables no_protect […] can you add what you commented to the commit description? -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:47:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
by Subrata Banik (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69041 ) Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It really is PCI BAR0, the device just gets hidden, so using index 0x10 is appropriate. in that case https://review.coreboot.org/c/coreboot/+/69041/1/src/soc/intel/meteorlake/p… is also wrong and pmc.c file resource allocator is wrong too https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/pm… Fundamentally you would like to reserve those resources/ranges and doesn’t really matter what index you are giving while reserving (take a look into systemagent.c file where we have given index incrementally) as it's *not* a PCI write into the said *index*, so, it doesn't break anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/69041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Gerrit-Change-Number: 69041 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in blobs[master]: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Rex-BC Chen, Yidi Lin. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/69086 ) Change subject: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/69086/comment/f3bb47fb_03c43bf9 PS1, Line 9: in MCUPM view > The efuse memory address is wrong for MCUPM to access. […] Done -- To view, visit https://review.coreboot.org/c/blobs/+/69086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04 Gerrit-Change-Number: 69086 Gerrit-PatchSet: 2 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:41:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Allow MCUPM to access the secure registers
by Liju-Clr Chen (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Allow MCUPM to access the secure registers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8188/devapc.c: https://review.coreboot.org/c/coreboot/+/69088/comment/f860bba5_c5faae10 PS1, Line 1557: SCP_SSPM_DOM, DOMAIN_2 > don't we need to keep SCP/SSPM in domain2? […] For MT8188, DEVAPC configures the hardwares(AP/others) as domain 0 by default and enables no_protection permssions for domain 0. The other domains are forbidden to access the registers. Later, we will investigate the requirements from the module owners to configure the different domains and enable the access permissions for the different hardwares. -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:40:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID
by Subrata Banik (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Ravishankar Sarawadi, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68305 ) Change subject: src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Gerrit-Change-Number: 68305 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 07:40:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022