coreboot-gerrit January 2022

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Change in coreboot[master]: ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60594 ) Change subject: ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax ...................................................................... ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax Replace `LNot (a)` with `!a`. Change-Id: I8de151e7df39a0282d032b8ca96c2d1b01014c3a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60594 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/ec/lenovo/h8/acpi/thermal.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 26b5df0..85cfdb5 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -73,7 +73,7 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LNot (MEB1) && LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128)) { + If (!MEB1 && LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128)) { Return (C2K(40)) } Store (1, MEB1) @@ -160,7 +160,7 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LNot (MEB2) && LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128)) { + If (!MEB2 && LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128)) { Return (C2K(40)) } Store (1, MEB2) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de151e7df39a0282d032b8ca96c2d1b01014c3a Gerrit-Change-Number: 60594 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec/acpi: Replace LNot() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60593 ) Change subject: ec/google/chromeec/acpi: Replace LNot() with ASL 2.0 syntax ...................................................................... ec/google/chromeec/acpi: Replace LNot() with ASL 2.0 syntax Replace `LNot (a)` with `!a`. Change-Id: I2bf5a09df831b66197c2a9af780c873290e12b42 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60593 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/acpi/battery.asl M src/ec/google/chromeec/acpi/ec.asl 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 8cbe710..ce4462d 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -201,7 +201,7 @@ // 2: BATTERY REMAINING CAPACITY // Store (BTRA, Local1) - If (Arg3 && ACEX && LNot (BFDC && BFCG)) { + If (Arg3 && ACEX && !(BFDC && BFCG)) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 10d930d..69d608b 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -489,7 +489,7 @@ */ Method (_Q09, 0, NotSerialized) { - If (LNot(Acquire (^PATM, 1000))) { + If (!Acquire (^PATM, 1000)) { /* Read sensor ID for event */ Store (^PATI, Local0) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bf5a09df831b66197c2a9af780c873290e12b42 Gerrit-Change-Number: 60593 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/quanta/it8518/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60592 ) Change subject: ec/quanta/it8518/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... ec/quanta/it8518/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: Ibf5bdb1b3c2524194089b27a8af61b84f517e117 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/ec/quanta/it8518/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 9c48442..5b51c89 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -67,7 +67,7 @@ { // EC Is not ready Sleep (5) - Decrement (Local0) + Local0-- If (LEqual (Local0, Zero)) { Break 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5bdb1b3c2524194089b27a8af61b84f517e117 Gerrit-Change-Number: 60592 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/quanta/ene_kb3940q/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60591 ) Change subject: ec/quanta/ene_kb3940q/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... ec/quanta/ene_kb3940q/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: I2105c22d15d4f078270911a7fa7290b3a9b6b841 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/ec/quanta/ene_kb3940q/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 12f0809..1f1cf97 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -194,7 +194,7 @@ Store(\_SB.CP00._PPC, Local0) If(Local0) { - Decrement(Local0) + Local0-- \PPCN () } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2105c22d15d4f078270911a7fa7290b3a9b6b841 Gerrit-Change-Number: 60591 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60590 ) Change subject: ec/google/chromeec/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... ec/google/chromeec/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: Ie2d5856316e2c8faac657c6caf79a46f099353be Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60590 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 3416633..8cbe710 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -22,7 +22,7 @@ While (LNotEqual (BTIX, Arg0)) { Sleep (1) - Decrement (Local0) + Local0-- If (LEqual (Local0, Zero)) { Return (One) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2d5856316e2c8faac657c6caf79a46f099353be Gerrit-Change-Number: 60590 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/gma/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60589 ) Change subject: drivers/intel/gma/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... drivers/intel/gma/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: I45c3d339652dd457cd4664ed03123eee2d7a5684 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60589 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/acpi/common.asl M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 0cf28fa..739b91c 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -40,7 +40,7 @@ Store (BRID (XBQC ()), Local0) If (LNotEqual (Local0, 2)) { - Decrement (Local0) + Local0-- } XBCM (DerefOf (BRIG[Local0])) } diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 99d2bc5..11d8fcd 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -83,7 +83,7 @@ Return (Ones) } } - Decrement (Local0) + Local0-- } Return (Ones) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3d339652dd457cd4664ed03123eee2d7a5684 Gerrit-Change-Number: 60589 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60588 ) Change subject: soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: I523c6b14c127ec7c0eb41078fb2eb92f42d74bd5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index ea9d5b4..6791e15 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -95,7 +95,7 @@ /* Read TOLUD */ And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) + GMAX-- GLEN = GMAX - GMIN + 1 /* Patch PM02 range based on Memory Size */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I523c6b14c127ec7c0eb41078fb2eb92f42d74bd5 Gerrit-Change-Number: 60588 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60587 ) Change subject: sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax Replace `Decrement (a)` with `a--`. Change-Id: Iae59333a910cc913bb28ed5436c124b2ab282435 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60587 Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/i82371eb/acpi/intx.asl M src/southbridge/intel/i82371eb/acpi/pirq.asl 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index c55ff33..f4fa928 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -40,7 +40,7 @@ /* Use lowest available IRQ */ \ FindSetRightBit(IRQM, Local0) \ if (Local0) { \ - Decrement(Local0) \ + Local0-- \ } \ Store(Local0, pinx) \ } \ diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index 176906a..eeab305 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -50,7 +50,7 @@ /* Use lowest available IRQ */ \ FindSetRightBit(IRQM, Local0) \ if (Local0) { \ - Decrement(Local0) \ + Local0-- \ } \ Store(Local0, pinx) \ } \ -- To view, visit https://review.coreboot.org/c/coreboot/+/60587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae59333a910cc913bb28ed5436c124b2ab282435 Gerrit-Change-Number: 60587 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Nico Huber (Code Review) 01 Jan '22

01 Jan '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz When using the default initial core display clock frequency, Magolor has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for magolor. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 66fc4ea..e0af22d 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -108,6 +108,9 @@ register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 11 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Nico Huber (Code Review) 01 Jan '22

01 Jan '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... soc/intel/jasperlake: Add CdClock frequency config Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 3 files changed, 31 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 87a98fb..256fa06 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -405,6 +405,26 @@ */ bool disable_external_bypass_vr; + /* + * Core Display Clock Frequency selection, FSP UPD CdClock values + 1 + * + * FSP will use the value to program clock frequency for core display if GOP + * is not run. Ex: the Chromebook normal mode. + * For the cases GOP is run, GOP will be in charge of the related register + * settings. + */ + enum { + CD_CLOCK_172_8_MHZ = 1, + CD_CLOCK_180_MHZ = 2, + CD_CLOCK_192_MHZ = 3, + CD_CLOCK_307_MHZ = 4, + CD_CLOCK_312_MHZ = 5, + CD_CLOCK_552_MHZ = 6, + CD_CLOCK_556_8_MHZ = 7, + CD_CLOCK_648_MHZ = 8, + CD_CLOCK_652_8_MHZ = 9, + } cd_clock; + }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 085148f7..a5bcd55 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -209,6 +209,15 @@ params->PchFivrExtVnnRailEnabledStates = 0; } + /* + * We intentionally want the default to be maximum value(0xff) to align with + * FSP, so we reserve the `0` value here to mean auto instead, and shift the + * other values by 1. + * + * Please refer to src/soc/intel/jasperlake/chip.h for the detail definition. + */ + params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index dd7db9d..02d9d76 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -875,11 +875,8 @@ UINT8 PavpEnable; /** Offset 0x0436 - CdClock Frequency selection - 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 - Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, - 9: 652.8 Mhz - 0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 - Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz + 0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz, + 7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default) **/ UINT8 CdClock; -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 29 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit January 2022